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| amd opteron? processor data sheet compatible with existing 32-bit code base ? including support for sse, sse2, mmx?, 3dnow!? technology and legacy x86 instructions ? runs existing operating systems and drivers ? local apic on-chip amd64 technology ? amd64 technology instruction set extensions ? 64-bit integer registers, 48-bit virtual addresses, 40- bit physical addresses ? eight new 64-bit integer registers (16 total) ? eight new 128-bit sse/sse2 registers (16 total) integrated memory controller ? low-latency, high-bandwidth ? 144-bit ddr sdram at 100, 133, 166, and 200 mhz (200mhz supported by rev c0 and later) hypertransport ? technology to i/o devices ? three links, 16-bits in each direction, each supports up to 1600 mt/s or 3.2 gb/s in each direction ? each link can connect to an i/o device or another processor 64-kbyte 2-way associative ecc-protected l1 data cache ? two 64-bit operations per cycle, 3-cycle latency 64-kbyte 2-way associative parity-protected l1 instruction cache ? with advanced branch prediction 1024-kbyte (1-mbyte) 16-way associative ecc-protected l2 cache ? exclusive cache architecture ? storage in addition to l1 caches machine check architecture ? includes hardware scrubbing of major ecc- protected arrays power management ? multiple low-power states ? system management mode (smm) ? acpi compliant electrical interfaces ? hypertransport technology: lvds-like differential, unidirectional ? ddr sdram: sstl_2 per jedec specification ? clock, reset, and test signals also use ddr sdram-like electrical specifications packaging ? 940-pin lidded ceramic micro pga ? 1.27-mm pin pitch ? 31x31 row pin array ? 40mm x 40mm ceramic substrate ? ceramic c4 die attach 144-bit ddr sdram memory three 16x16-bit 1600 mt/s (6.4 gigabytes/s) max each (128 bits + 16 bits ecc) amd opteron ? processor hypertransport ? links 23932 publication # 3.09 revision: february 2004 issue date:
23932 rev. 3.09 february 2004 amd opteron? processor data sheet trademarks amd, the amd arrow logo, amd athlon, amd opteron and combinations thereof, and 3dnow! are trademarks of advanced micro devices, inc. hypertransport is a licensed trademark of the hypertransport technology consortium. mmx is a trademark of intel corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ( ? amd ? ) products. amd makes no rep- resentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd ? s standard terms and condi- tions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products inc luding, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellect ual property right. amd ? s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure o f amd ? s prod- uct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves t he right to discontinue or make changes to its products at any time without notice. ? 2002, 2003, 2004 advanced micro devices, inc. all rights reserved. contents 3 23932 rev 3.09 february 2004 amd opteron ? processor data sheet contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 amd opteron? processor overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 instruction set support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 internal cache structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 2.2.1 level 1 caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 level 2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 2.3 error handling (machine check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 northbridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 hypertransport ? technology overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1.1 link initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1.2 hypertransport ? technology transfer speeds . . . . . . . . . . . . . . . . . . . . . . 11 2.4.2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.2.1 memory pin interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2.2 dram operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.2.3 dram power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.2.4 chip kill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.2.5 main memory hardware scrubbing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 stpclk/stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 pwrok . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 reset_l and memreset_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 thermal diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 thermtrip_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 contents amd opteron ? processor data sheet 23932 rev 3.09 february 2004 6.1 hypertransport ? technology pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 ddr sdram memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3 miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4 pin states at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2 hypertransport ? technology interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.2.2 reference information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.3 ddr sdram and miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3.2 ac operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.4 clock pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.5 power-up signal sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.6 reference information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 7.7 thermal diode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.8 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.8.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.8.2 thermal power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.8.3 power supply relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.8.3.1 sequencing relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.8.3.2 sequencing relationships: signals to power supplies (stress conditions) . . 75 7.8.3.3 power failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.8.3.4 unused links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 list of figures 5 23932 rev 3.09 february 2004 amd opteron ? processor data sheet list of figures figure 1. amd opteron ? processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. amd opteron ? processor micro pga ? top view, left side . . . . . . . . . . . . . . . . . 22 figure 3. amd opteron ? processor micro pga ? top view, right side . . . . . . . . . . . . . . . . 23 figure 4. slew rate measurement example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 5. memclk output skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 6. memdqs timing parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 7. dss/tdsh timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 8. tdqsqv/tdqsqiv timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 9. memadd/cmd to memclk timing parameter (registered dimms) . . . . . . . . . . 61 figure 10. memdqs edge arrival relative to dqs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. memreset_l and memcke_lo/up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 12. power-up signal sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 13. sequencing relationships for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 14. ceramic micro pin grid array package: top, side, and bottom views . . . . . . . . . . . 77 6 list of tables amd opteron ? processor data sheet 23932 rev 3.09 february 2004 list of tables table 1. dram interface speed vs. cpu core clock multiplier . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. total memory sizes per chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. processor capabilities mapped to acpi states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. pin list by name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. pin description table definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6. hypertransport ? technology pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 7. ddr sdram memory interface pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 8. clock pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 9. miscellaneous pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10. vid[4:0] encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 11. jtag pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12. debug pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 13. reset pin state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14. absolute maximum ratings for amd opteron ? processor. . . . . . . . . . . . . . . . . . . . 47 table 15. dc operating conditions for hypertransport ? technology interface . . . . . . . . . . . 48 table 16. ac operating conditions for hypertransport ? technology interface . . . . . . . . . . . 49 table 17. internal termination for hypertransport ? technology interface . . . . . . . . . . . . . . . 50 table 18. dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 table 19. ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 20. input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 21. slew rate of ddr sdram signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 22. package routing skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. electrical ac timing characteristics for ddr sdram signals . . . . . . . . . . . . . . . . 56 table 24. dc operating conditions for clkin_h/l and fbclkout_h/l pins . . . . . . . . . . . 63 table 25. ac operating conditions for clkin_h/l and fbclkout_h/l pins . . . . . . . . . . . 64 table 26. memreset_l and memcke_lo/up initialization timing . . . . . . . . . . . . . . . . . . 66 table 27. memcke_lo/up delay from memreset_l during exit from self-refresh . . . . 66 table 28. internal termination for miscellaneous pins interface. . . . . . . . . . . . . . . . . . . . . . . . . 68 list of tables 7 23932 rev 3.09 february 2004 amd opteron ? processor data sheet table 29. external required circuits (pins not normally used in system) . . . . . . . . . . . . . . . . 69 table 30. thermal diode specification revision and frequency guide . . . . . . . . . . . . . . . . . . . 70 table 31. thermal diode specifications for amd opteron ? processor (revision and frequency dependent, see table 30)70 table 32. thermal diode specifications for amd opteron ? processor (revision and frequency dependent, see table 30)71 table 33. combined ac and dc operating conditions for power supplies . . . . . . . . . . . . . . . . 72 table 34. sequencing relationships for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8 revision history amd opteron ? processor data sheet 23932 rev 3.09 february 2004 revision history date revision description february 2004 3.09 added clkin jitter specification to table 26. updated note for vddio to vtt stress during power up/down for table 35. added note to require vtt tracking vddio/2 for table 35. clarified power supply relationship note for table 35. revised vdd specifications in table 34. updated notes in table 29 to clarify termination usage. changed ref from 2.5v to vddio in table 6. separated and revised vid voh paramter in table 19. moved dimm speed/ loading table out of this document novermber 2003 3.06 removed extended range temp sensor requirement. new logo. storage temp change in section 7.1. ht termination change in table 18. added tcase thermal diode specifications for specific revisions and frequencies in section 7.7. updated tdo and dbrdy pull-up info in table 30. changed title of design guides. added pwrok clarification in sequencing relationships section. added ddr400 support. general clean-up, added rev c information and separated power and thermal specifications (moved to a separate document). updated iddio2 i/o current specification in table 32, changed nc_ae3 to nc_ae13 in table 30, removed separate thermtrip_l electrical section and grouped with ddr pin electricals. clarified ecc and chip kill descriptions in sections 2.4.2.4 through 2.4.2.5. corrected amd64 naming. april 2003 3.00 initial release. chapter 1 amd opteron ? processor overview 9 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 1 amd opteron ? processor overview the amd opteron ? processor is designed for high-performance workstation and server applications. it provides three high-performance hypertransport ? links to i/o, as well as a 128-bit high-performance ddr sdram memory controller. a block diagram of the amd opteron processor is shown in figure 1. figure 1. amd opteron ? processor block diagram cpu core 1-mbyte l2 cache hypertransport ? interface ddr sdram interface northbridge 3 x 16/16 400? 1600 mt/s 128-bits ddr sdram 100/133/166/200 mhz 16-bits ecc memclk_lo_h/l[3:0] memcke_up memreset_l memcs_l[7:0] memadd[13:0] membank[1:0] memras_l memcas_l memwe_l memdqs[35:0] memdata[127:0] memcheck[15:0] memzn memzp memvref l0_clkin_h/l[1:0] l0_ctlin_h/l[0] l0_cadin_h/l[15:0] l0_clkout_h/l[1:0] l0_ctlout_h/l[0] l0_cadout_h/l[15:0] ldtstop_l l0_ref0 l0_ref1 clkin_h/l fbclkout_h/l plls jtag tdi tdo tck tms trst_l dbreq_l dbrdy vdda reset_l pwrok control vid[4:0] thermda thermdc thermtrip_l corefb_h/l and debug and clocks 64-kbyte l1 i-cache 64-kbyte l1 d-cache memclk_up_h/l[3:0] l1_clkin_h/l[1:0] l1_ctlin_h/l[0] l1_cadin_h/l[15:0] l1_clkout_h/l[1:0] l1_ctlout_h/l[0] l1_cadout_h/l[15:0] l2_clkin_h/l[1:0] l2_ctlin_h/l[0] l2_cadin_h/l[15:0] l2_clkout_h/l[1:0] l2_ctlout_h/l[0] l2_cadout_h/l[15:0] memcke_lo presence_det 10 functional description chapter 2 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 2 functional description 2.1 instruction set support the amd opteron ? processor supports the standard x86-instruction set defined in the amd64 architecture programmer ? s manual, volumes 3 ? 5, order# 24594. in addition, the processor supports the following extensions to the standard x86 instruction set, which are described in the same volume set: amd64 instructions mmx ? and 3dnow! ? technology instructions sse and sse2 instructions 2.2 internal cache structures the amd opteron processor implements internal caching structures as described in the following sections. 2.2.1 level 1 caches the l1 data cache (l1 d-cache) contains 64 kbytes of storage organized as two-way set associative. the l1 data cache is protected with ecc. two simultaneous 64-bit operations (load, store, or combination) are supported. the l1 instruction cache (l1 i-cache) contains 64 kbytes of storage organized as two-way associative. the l1 instruction cache is protected with parity. 2.2.2 level 2 cache the l2 cache contains both instruction and data stream information. it is organized as 16-way set- associative. the l2 cache data and tag store is protected with ecc. when a given cache line in the l2 cache contains instruction stream information, the ecc bits associated with the given line are used to store predecode and branch prediction information. 2.3 error handling (machine check) the amd opteron processor implements the standard x86 machine check architecture as defined in the amd64 architecture programmer ? s manual, volume 2 , order# 24593, and the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? processors , order# 26094. chapter 2 functional description 11 23932 rev 3.09 february 2004 amd opteron ? processor data sheet the machine check architecture is defined with ecc single-bit detection/correction and double-bit detection for the following arrays: l1 data cache storage l2 data cache storage l2 data cache tag instruction cache dram. see ? memory controller ? on page 11. 2.4 northbridge the northbridge logic in the amd opteron processor refers to the hypertransport ? technology interface and the memory controller and their respective interfaces to the cpu cores. these interfaces are described in more detail in the following sections. 2.4.1 hypertransport ? technology overview the amd opteron processor includes three 16-bit hypertransport technology interfaces capable of operating up to 1600 mega-transfers per second (mt/s) with a resulting bandwidth of up to 6.4 gbytes/s (3.2 gbytes/s in each direction). the amd opteron processor supports hypertransport technology synchronous clocking mode. refer to the hypertransport ? i/o link specification (www.hypertransport.org) for details of link operation. 2.4.1.1 link initialization the hypertransport ? i/o link specification details the negotiation that occurs at power-on to determine the widths and rates used with the link. refer also to the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? processors , order# 26094, for information about link initialization and setup of routing tables. refer to the amd athlon ? 64 fx and amd opteron ? processor motherboard design guide , order# 25180, for details on the proper hypertransport technology signal termination resistor values. 2.4.1.2 hypertransport ? technology transfer speeds the hypertransport link of the amd opteron processor is capable of operating at 400, 800, 1200, and 1600 mt/s. the link transfer rate is determined during the software configuration of the system, as specified in the hypertransport ? i/o link specification . 2.4.2 memory controller the processor ? s memory controller provides a programmable interface to a variety of standard registered ddr sdram dimm configurations. refer to the bios and kernel developer ? s guide for 12 functional description chapter 2 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 the amd athlon ? 64 and amd opteron ? processors , order# 26094, for supported dram speeds under specific loading conditions. self-refresh mode the controller provides programmable control of dram timing parameters to support the following memory speeds: ? 100 mhz (ddr200) pc-1600 dimms ? 133 mhz (ddr266) pc-2100 dimms ? 166 mhz (ddr333) pc-2700 dimms ? 200 mhz (ddr400) pc-3200 dimms* dram devices that are 4, 8 and 16 bits wide dimm sizes from 32 mbytes (using 64mb x16 drams) to 4 gbytes (using a stacked dimm with 1gb x4 drams) interleaving memory within dimms stacked registered dimms ecc checking with single-bit correction and double-bit detection chip kill ecc allows single symbol correction and double symbol detection may be configured for 32-byte or 64-byte burst length programmable page-policy: ? supports up to 16 open pages total across all chip-selects ? statically idle open-page time ? optional dynamic precharge control based on page-hit/miss history * ddr400 supported by rev c0 and later, refer to amd opteron tm processor power and thermal data sheet, order# 30417, for silicon revision determination for programming information and specific details of the features listed above, refer to the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? processors , order# 26094. 2.4.2.1 memory pin interface the memory controller of the amd opteron processor supports registered ddr sdram dimms. the following list applies to the pin interface: the memreset_l pin is required for registered dimms and is used to reset the register as required to support the suspend to ram power management state (acpi s3). the memory controller can be configured to support either 64-bit or 128-bit memory interfaces. refer to the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? chapter 2 functional description 13 23932 rev 3.09 february 2004 amd opteron ? processor data sheet processors , order# 26094, for restrictions based on ddr sdram speed. a 64-bit memory system can support up to four dimms, each 64-bits wide a 128-bit memory system can support up to eight dimms, each 64-bits wide, and must be populated in even numbered pairs as described in the amd athlon ? 64 fx and amd opteron ? processor motherboard design guide , order# 25180. registered dimms configured with x4 drams require an additional 16 dqs pins without ecc support or 18 dqs pins with ecc support. the processor ? s memory controller provides a total of 36 dqs pins to accommodate this requirement. the additional dqs pins can be connected to the dimm data mask (dm) pins when connected to x8 or x16 dimms. dimms populated with x4 devices normally connect the dram data mask (dm) pins to vss. 2.4.2.2 dram operation at power-on reset, the memcke_lo/up and memreset_l pins are driven low while the processor plls are ramping. clocks are driven on the memclk_lo_h/l[3:0] and memclk_up_h/l[3:0] pins only after bios programs the appropriate clock ratio value in the memory controller configuration registers. the actual dram frequency may vary for some speeds based on the cpu clock multiplier, as shown in table 1 on page 13 (the memory controller automatically adjusts refresh counters at all speeds as required to meet the device refresh specifications). refer to ? power-up signal sequencing ? on page 65 for further details on the sequencing of the memreset_l and memcke_lo/up pins. table 1. dram interface speed vs. cpu core clock multiplier notes: multiplier core frequency dram frequency 100 mhz 133 mhz 166 mhz 200 mhz 1 4 800 mhz 100.00 133.33 160.00 160.00 5 1000 mhz 100.00 125.00 166.66 200.00 6 1200 mhz 100.00 133.33 150.00 200.00 7 1400 mhz 100.00 127.27 155.55 200.00 8 1600 mhz 100.00 133.33 160.00 200.00 9 1800 mhz 100.00 128.57 163.63 200.00 10 2000 mhz 100.00 133.33 166.66 200.00 11 2200 mhz 100.00 129.41 157.14 200.00 12 2400 mhz 100.00 133.33 160.00 200.00 13 2600 mhz 100.00 130.00 162.50 200.00 14 functional description chapter 2 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 1. ddr400 (200mhz) supported by rev c0 and later. refer to the amd opteron ? processor power and thermal data sheet, order# 30417 for silicon revision determination. table 2 on page 15 lists the maximum memory sizes per chip-select for the various supported dram device configurations. note that for dimms using two chip-selects, the total memory size per dimm is doubled. refer to the amd athlon ? 64 fx and amd opteron ? processor motherboard design guide , order# 25180, for details on the connection scheme for registered dimms in an amd opteron processor system. chapter 2 functional description 15 23932 rev 3.09 february 2004 amd opteron ? processor data sheet table 2. total memory sizes per chip select the controller supports programmable timing and refresh as described in the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? processors , order# 26094. auto- refresh is supported and is staggered by t rfc across chip-selects to reduce system noise. unpopulated dimm slots are not refreshed. 2.4.2.3 dram power management the memory controller supports self-refresh mode to accommodate various power management states such as acpi s1 and s3 states. the memreset_l pin is provided for resetting the registers on registered ddr sdram dimms as required for the s3 (suspend-to-ram) power management state. 2.4.2.4 chip kill in chip kill mode the memory controller can correct single symbol errors and detect double symbol errors across the 128-bit wide data path. this feature optionally takes the place of normal ecc error detection and correction. operating the memory controller with chip kill enabled will result in a two devices used on dimms size per cs 64 m-bit (4m x4-bits x4 banks) 128 mbyte 64 m-bit (2m x8-bits x4 banks) 64 mbyte 64 m-bit (1m x16-bits x4 banks) 32 mbyte 128 m-bit (8m x4-bits x4 banks) 256 mbyte 128 m-bit (4m x8-bits x4 banks) 128 mbyte 128 m-bit (2m x16-bits x4 banks) 64 mbyte 256 m-bit (16m x4-bits x4 banks) 512 mbyte 256 m-bit (8m x8-bits x4 banks) 256 mbyte 256 m-bit (4m x16-bits x4 banks) 128 mbyte 512 m-bit (32m x4-bits x4 banks) 1 gbyte 512 m-bit (16m x8-bits x4 banks) 512 mbyte 512 m-bit (8m x16-bits x4 banks) 256 mbyte 1 g-bit (64m x4-bits x4 banks) 2 gbyte 1 g-bit (32m x8-bits x4 banks) 1 gbyte 1 g-bit (16m x16-bits x4 banks) 512 mbyte 16 functional description chapter 2 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 clock latency penalty on memory access due to the detection, correction, and data containment overhead of operating in this mode. 2.4.2.5 main memory hardware scrubbing the memory controller scrubs the main memory arrays to prevent the build up of soft errors. any correctable or non-correctable errors are logged to the machine check logs and non-correctable errors can be programmed to invoke the machine check interrupt. a correctable error is a single-bit error in normal ecc mode or a single symbol error in chip kill mode. there are two modes of main memory scrubbing that can be used independently or combined, as described in the following sections. 2.4.2.5.1 sequential scrubbing in this mode, the scrubber sequentially proceeds through main memory, performing a read-write cycle or a read-modify-write cycle if a correctable error is found. the scrubber scrubs one cache line on each scrub interval that is programmable from 40 ns to 84 ms. 2.4.2.5.2 source correction scrubbing in this mode, the scrubber is directed to scrub any cache line that is the source of any corrected error during normal accesses. during normal operation when source correction scrubbing is disabled, single-bit errors are corrected on the fly and the corrected data is passed without updating the source memory location. when source scrubbing is enabled the scrubber also corrects the source memory location. 2.4.2.5.3 sequential plus source correction scrubbing when both sequential and source correction scrubbing are enabled, the scrubber sequentially proceeds through main memory. if a correctable error is detected during normal operation, the scrubber is redirected to the location of the error, and after it corrects that location in main memory it resumes sequential scrubbing at the previous location. chapter 3 power management 17 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 3 power management the amd opteron ? processor provides the following power management features designed to be compliant with the advanced configuration and power interface (acpi) specification and hypertransport ? technology: halt state with associated programmable power savings stpclk/stop grant protocol capable of supporting eight distinct versions of stop grant ldtstop_l signal support memory controller and host bridge power management voltage plane isolation based upon pwrok signal low-power state while reset_l signal is asserted on-die thermal diode table 3 maps processor capabilities to acpi states. 3.1 halt when the hlt instruction is executed, the processor stops program execution and issues a halt special cycle. the power savings associated with the halt state are determined by configuration registers in the processor (refer to the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? processors , order# 26094, for details of these configuration registers). the cpu clock grid frequency can be divided down in the absence of probe activity that would force the processor caches to be snooped. the cpu clock grid is automatically brought to full frequency when probe activity is present and returned to the low-power state when probe activity ceases. table 3. processor capabilities mapped to acpi states acpi state processor c1 halt passive cooling passive cooling is supported by stop grant (throttling). s1 stop grant. in response to ldtstop_l assertion, memory is placed in self-refresh mode and the host bridge and memory controller are placed into a low-power state. s3 processor core and hypertransport ? technology voltage planes are not powered. ddr sdram interface remains powered and holds memory in self-refresh mode. s4, s5, g3 all power is removed from the processor. 18 power management chapter 3 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 if a stpclk assertion message is received while the processor is in the halt state, the processor enters the stop grant state and issues a stop grant special cycle. when a stpclk deassertion message is received, the processor exits the stop grant state and returns to the halt state. the processor exits the halt state in response to pwrok deassertion, reset_l assertion, init, nmi, smi, or any unmasked interrupt received over the hypertransport link. 3.2 stpclk/stop grant when the processor recognizes the stpclk assertion message, it enters the stop grant state on the next instruction boundary and issues a stop grant special cycle. the power savings associated with the stop grant state are determined by configuration registers in the processor. the power savings mechanisms associated with the stop grant state include the following: cpu clock grid divisor applied in the absence of probe activity. if probe activity that requires a cache snoop occurs while the processor is in the stop grant state, the clock grid is ramped back up to service the probe. when probe activity ceases, the cpu clock grid is ramped back down again. placing system memory into self-refresh mode in response to ldtstop_l signal assertion. ramping the processor host bridge/memory controller clock grid down in response to ldtstop_l signal assertion. changing hypertransport link width and/or link frequency in response to ldtstop_l signal assertion. the processor exits the stop grant state when it receives the following: a stpclk deassertion message. reset_l pin asserted or an init assertion message. pwrok is deasserted. if the ldtstop_l signal is asserted after the processor is in the stop grant state, then ldtstop_l must be deasserted, and the hypertransport link must be re-initialized before a stpclk deassertion message can be received by the processor to bring the processor out of the stop grant state. the processor ? s host bridge ensures that stpclk messages are passed to the cpu prior to the subsequent i/o response to the cycle that caused stpclk assertion as long as the subsequent i/o response message has the passpw bit clear and the unit id of the response matches the unit id of the stpclk message. 3.3 pwrok when pwrok is deasserted, the processor performs the following steps: isolates its vddio- and vtt-powered logic from all other internal logic to prevent leakage chapter 3 power management 19 23932 rev 3.09 february 2004 amd opteron ? processor data sheet current paths between power planes. tristates all ddr sdram i/o pins except for the memcke_lo/up and memreset_l out- puts, which are driven low. drives its vid[4:0] outputs to the value that selects the startup core voltage level. 3.4 reset_l and memreset_l when reset_l is asserted, the processor performs the following steps: the processor core is held in a low-power state. the memcke_lo/up and memreset_l outputs are forced low. after reset_l is deasserted, bios must program the appropriate clock divisor in the memory con- troller configuration registers, causing the memclk_lo_h/l[3:0] and memclk_up_h/l[3:0] clocks to be driven. refer to ? power-up signal sequencing ? on page 65 for details of reset_l and memreset_l sequencing during initial power-on. 3.5 thermal diode the processor provides an on-die thermal diode with anode and cathode brought out to processor pins. this diode can be read by an external temperature sensor to determine the processor ? s temperature. refer to the amd athlon ? 64 fx and amd opteron ? processor motherboard design guide , order# 25180, for details on connecting the thermal diode. 3.6 thermtrip_l the amd opteron processor provides a hardware-enforced thermal protection mechanism. when the processor ? s die temperature exceeds a specified temperature, the processor is designed to protect itself from over-temperature conditions by stopping its internal clocks and asserting the thermtrip_l output. thermtrip_l assertion is only valid when pwrok is asserted and reset_l is deasserted. if the processor ? s die temperature still exceeds the thermal trip point when reset_l is deasserted, thermtrip_l will immediately be reasserted and the processor ? s internal clocks will be stopped. thermtrip_l assertion indicates the processor die temperature has exceeded normal operating parameters. pwrok must be deasserted in response to a thermtrip_l assertion to help ensure proper processor operation. 20 power management chapter 3 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 chapter 4 connection diagrams 21 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 4 connection diagrams the pinout for the amd opteron ? processor is illustrated in this chapter. the ball map is divided into two parts. figure 2 on page 22 shows the left portion of the top view, and figure 3 on page 23 shows the right portion of the top view. the pin designations are defined in chapter 5. table 4 on page 26 lists the pins alphabetically by pin name. 22 connection diagrams chapter 4 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 figure 2. amd opteron ? processor micro pga ? top view, left side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a l1_cadout_h[0] l1_cadout_l[0] l1_cadout_h[2] l1_cadout_l[2] l1_clkout_h[0] l1_clkout_l[0] l1_cadout_h[5] l1_cadout_l[5] l1_cadout_h[7] l1_cadout_l[7] l1_ctlin_l[0] l1_ctlin_h[0] l1_cadin_l[6] b vss l1_cadout_h[1] vdd l1_cadout_h[3] vss l1_cadout_h[4] vdd l1_cadout_h[6] vss l1_ctlout_h[0] vdd l1_cadin_l[7] vss c vdda1 vdda3 l1_cadout_l[8] l1_cadout_l[1] l1_cadout_l[10] l1_cadout_l[3] l1_clkout_l[1] l1_cadout_l[4] l1_cadout_l[13] l1_cadout_l[6] l1_cadout_l[15] l1_ctlout_l[0] nc_c13 l1_cadin_h[7] l1_cadin_h[14] d l0_ref0 vdda2 l1_cadout_h[8] vdd l1_cadout_h[10] vss l1_clkout_h[1] vdd l1_cadout_h[13] vss l1_cadout_h[15] vdd nc_d13 vss l1_cadin_l[14] e l0_ref1 vss l1_cadout_h[9] l1_cadout_l[9] l1_cadout_h[11] l1_cadout_l[11] l1_cadout_h[12] l1_cadout_l[12] l1_cadout_h[14] l1_cadout_l[14] nc_e11 nc_e12 l1_cadin_l[15] l1_cadin_h[15] l1_cadin_l[13] f vss vss vss vdd nc_f7 vss vid[3] vss vdd pwrok vss vss vdd g l0_cadin_h[1] l0_cadin_l[0] l0_cadin_h[0] vss l0_cadin_h[8] nc_g6 vdd dbrdy vid[4] vid[2] vid[0] reset_l vss nc_g14 vss h l0_cadin_l[1] vdd l0_cadin_h[9] l0_cadin_l[9] l0_cadin_l[8] vss nc_h7 vldt_1 nc_h9 vldt_1 vid[1] nc_h12 nc_h13 nc_h14 vss j l0_cadin_h[3] l0_cadin_l[2] l0_cadin_h[2] vdd l0_cadin_h[10] ldtstop_l dbreq_l vss vldt_1 vss vldt_1 vss vdd vss vldt_1 k l0_cadin_l[3] vss l0_cadin_h[11] l0_cadin_l[11] l0_cadin_l[10] vdd coresense_h nc_k8 vss vldt_1 vss vdd vss vldt_1 vss l l0_cadin_h[4] l0_clkin_l[0] l0_clkin_h[0] vss l0_clkin_h[1] corefb_l corefb_h nc_l8 vdd vss vdd vss vdd vss vdd m l0_cadin_l[4] vdd l0_cadin_h[12] l0_cadin_l[12] l0_clkin_l[1] vss vss vldt_0 vss vdd vss vdd vss vdd vss n l0_cadin_h[6] l0_cadin_l[5] l0_cadin_h[5] vdd l0_cadin_h[13] nc_n6 vldt_0 vss vdd vss vdd vss vdd vss vdd p l0_cadin_l[6] vss l0_cadin_h[14] l0_cadin_l[14] l0_cadin_l[13] vdd vss vldt_0 vss vdd vss vdd vss vdd vss r l0_ctlin_h[0] l0_cadin_l[7] l0_cadin_h[7] vss l0_cadin_h[15] nc_r6 vldt_0 vss vdd vss vdd vss vdd vss vdd t l0_ctlin_l[0] vdd nc_t3 nc_t4 l0_cadin_l[15] vss nc_t7 vdd vss vdd vss vdd vss vdd vss u l0_cadout_l[7] l0_ctlout_h[0] l0_ctlout_l[0] vdd nc_u5 nc_u6 vldt_0 vss vdd vss vdd vss vdd vss vdd v l0_cadout_h[7] vss l0_cadout_l[15] l0_cadout_h[15] nc_v5 vdd vss vldt_0 vss vdd vss vdd vss vdd vss w l0_cadout_l[5] l0_cadout_h[6] l0_cadout_l[6] vss l0_cadout_l[14] nc_w6 vldt_0 vss vdd vss vdd vss vdd vss vdd y l0_cadout_h[5] vdd l0_cadout_l[13] l0_cadout_h[13] l0_cadout_h[14] vss vss vldt_0 vss vdd vss vdd vss vdd vss aa l0_clkout_l[0] l0_cadout_h[4] l0_cadout_l[4] vdd l0_cadout_l[12] nc_aa6 vldt_0 vss vdd vss vdd vss vdd vss vdd ab l0_clkout_h[0] vss l0_clkout_l[1] l0_clkout_h[1] l0_cadout_h[12] vdd vss vdd vss vldt_2 vss vdd vss vldt_2 vss ac l0_cadout_l[2] l0_cadout_h[3] l0_cadout_l[3] vss l0_cadout_l[11] nc_ac6 vldt_2 vss vldt_2 vss vdd vss vldt_2 ad l0_cadout_h[2] vdd l0_cadout_l[10] l0_cadout_h[10] l0_cadout_h[11] vss trst_l vldt_2 vss vldt_2 vss vdd vss vdd vss ae l0_cadout_l[0] l0_cadout_h[1] l0_cadout_l[1] vdd l0_cadout_l[9] tms tck tdo nc_ae9 nc_ae10 nc_ae11 nc_ae12 nc_ae13 nc_ae14 thermtrip_l af l0_cadout_h[0] vss l0_cadout_l[8] l0_cadout_h[8] l0_cadout_h[9] vdd tdi vss nc_af9 vdd nc_af11 vss nc_af13 vdd nc_af15 ag nc_ag1 vss l2_cadin_h[8] l2_cadin_l[8] l2_cadin_h[10] l2_cadin_l[10] l2_clkin_h[1] l2_clkin_l[1] l2_cadin_h[13] l2_cadin_l[13] l2_cadin_h[15] l2_cadin_l[15] nc_ag13 nc_ag14 l2_cadout_l[14] ah thermdc nc_ah2 vss l2_cadin_l[9] vdd l2_cadin_l[11] vss l2_cadin_l[12] vdd l2_cadin_l[14] vss nc_ah12 vdd l2_cadout_h[15] vss aj thermda nc_aj2 l2_cadin_h[0] l2_cadin_h[9] l2_cadin_h[2] l2_cadin_h[11] l2_clkin_h[0] l2_cadin_h[12] l2_cadin_h[5] l2_cadin_h[14] l2_cadin_h[7] nc_aj12 l2_ctlout_l[0] l2_cadout_l[15] l2_cadout_l[6] ak presence_det l2_cadin_l[0] vdd l2_cadin_l[2] vss l2_clkin_l[0] vdd l2_cadin_l[5] vss l2_cadin_l[7] vdd l2_ctlout_h[0] vss l2_cadout_h[6] al l2_cadin_h[1] l2_cadin_l[1] l2_cadin_h[3] l2_cadin_l[3] l2_cadin_h[4] l2_cadin_l[4] l2_cadin_h[6] l2_cadin_l[6] l2_ctlin_h[0] l2_ctlin_l[0] l2_cadout_l[7] l2_cadout_h[7] l2_cadout_l[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 chapter 4 connection diagrams 23 23932 rev 3.09 february 2004 amd opteron ? processor data sheet figure 3. amd opteron ? processor micro pga ? top view, right side 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 l1_cadin_h[6] l1_cadin_l[4] l1_cadin_h[4] l1_cadin_l[3] l1_cadin_h[3] l1_cadin_l[1] l1_cadin_h[1] vddio memdata[4] memdata[1] memdata[6] memdata[2] memdata[3] memdata[9] a l1_cadin_l[5] vdd l1_clkin_l[0] vss l1_cadin_l[2] vdd l1_cadin_l[0] vss memdata[0] memdqs[9] vss memdata[7] memdata[8] vss memdata[13] b l1_cadin_h[5] l1_cadin_h[12] l1_clkin_h[0] l1_cadin_h[11] l1_cadin_h[2] l1_cadin_h[9] l1_cadin_h[0] vddio memdata[5] memdqs[0] memdata[71] memdata[72] memdata[12] memdqs[1] memdqs[10] memdata[14] c vdd l1_cadin_l[12] vss l1_cadin_l[11] vdd l1_cadin_l[9] vss vss memdata[69] memdqs[18] vddio memdata[76] vddio memdata[77] vss memdata[15] d l1_cadin_h[13] l1_clkin_l[1] l1_clkin_h[1] l1_cadin_l[10] l1_cadin_h[10] l1_cadin_l[8] l1_cadin_h[8] vddio memdata[65] memdata[70] memdata[67] memdata[73] memdqs[19] memdqs[28] memdata[10] memdata[11] e vss vss vdd vdd vtt vtt memvref0 memdata[68] memdqs[27] memdata[66] memdata[78] memdata[79] memdata[74] memdata[20] memdata[16] memdata[17] f clkin_h vss fbclkout_h vtt memclk_up_h[3] memclk_up_l[3] vss memdata[64] vss memreset_l vddio memdata[75] vddio memdata[84] vss memdata[21] g clkin_l vss fbclkout_l vtt vddio memclk_lo_h[3] memcke_up memcke_lo memdata[80] memdata[81] memdata[85] memdqs[2] memdqs[11] memdata[18] h vldt_1 vss vss vtt vss vddio vss memclk_lo_l[3] memadd[12] memadd[11] memdqs[20] memdqs[29] memdata[82] memdata[22] memdata[23] memdata[19] j vldt_1 vss vdd vss vddio vss vddio memadd[9] vss memadd[7] vddio memdata[86] vddio memdata[87] vss memdata[24] k vss vdd vss vddio vss vddio vss memadd[8] memclk_up_h[1] memclk_up_l[1] memdata[83] memdata[88] memdata[92] memdata[28] memdata[29] memdata[25] l vdd vss vdd vss vdd vss vddio nc_m23 memadd[5] memadd[6] memdata[93] memdata[89] memdqs[21] memdqs[3] memdqs[12] memdata[30] m vss vdd vss vdd vss vddio vss memadd[3] vss memadd[4] vddio memdqs[30] vddio memdata[94] vss memdata[26] n vdd vss vdd vss vdd vss vddio memadd[2] memcheck[13] memcheck[12] memdata[90] memdata[91] memdata[95] memdata[27] memche ck [4] memdata[31] p vss vdd vss vdd vss vddio vss memclk_up_h[0] memcheck[8] memcheck[9] memcheck[10] memdqs[35] memdqs[26] memcheck[1] memche ck [5] memcheck[0] r vdd vss vdd vss vdd vss vddio memclk_up_l[0] vss memadd[1] vddio memcheck[11] vddio memcheck[14] vss memdqs[8] t vss vdd vss vdd vss vddio vss vddio memclk_lo_l[0] memclk_lo_h[0] memdata[100] memdata[96] memcheck[15] memcheck[6] memche ck [2] memdqs[17] u vdd vss vdd vss vdd vss vddio nc_v23 memadd[10] memadd[0] memdqs[22] memdata[97] memdata[101] memdata[32] memche ck [7] memcheck[3] v vss vdd vss vdd vss vddio vss membank[0] vss membank[1] vddio memdata[98] vddio memdqs[31] vss memdata[36] w vdd vss vdd vss vdd vss vddio memclk_lo_h[1] memwe_l memras_l memdata[99] memdata[103] memdata[102] memdqs[4] memdata[33] memdata[37] y vss vdd vss vddio vss vddio vss memclk_lo_l[1] memcs_l[0] memcas_l memdata[109] memdata[104] memdata[108] memdata[38] memdata[34] memdqs[13] aa vldt_2 vss vdd vss vddio vss vddio vddiofb_h vss memcs_l[1] vddio memdqs[32] vddio memdata[105] vss memdata[39] ab vldt_2 vss vtt vtt vss vddio vss vddiofb_l memcs_l[3] memcs_l[2] memdata[110] memdata[106] memdqs[23] memdata[40] memdata[44] memdata[35] ac vdd vss memclk_lo_l[2] memclk_lo_h[2] vddio memcs_l[7] memcs_l[5] memcs_l[4] memdata[112] memdata[111] memdata[107] memdqs[14] memdata[41] memdata[45] ad memzp vss vtt vtt memclk_up_l[2] memclk_up_h[2] vss memadd[13] vss memcs_l[6] vddio memdata[113] vddio memdata[116] vss memdqs[5] ae vss memzn vtt vtt_sense vddio_sense vss memvref1 memdata[123] memdqs[25] memdata[121] memdata[118] memdqs[33] memdata[117] memdata[43] memdata[46] memdata[42] af l2_cadout_h[14] l2_cadout_l[12] l2_cadout_h[12] l2_cadout_l[11] l2_cadout_h[11] l2_cadout_l[9] l2_cadout_h[9] vddio memdata[127] memdqs[34] memdata[125] memdata[119] memdqs[24] memdata[52] memdata[48] memdata[47] ag l2_cadout_h[13] vdd l2_clkout_h[1] vss l2_cadout_h[10] vdd l2_cadout_h[8] vss memdata[122] memdata[126] vddio memdata[124] vddio memdata[114] vss memdata[49] ah l2_cadout_l[13] l2_cadout_l[4] l2_clkout_l[1] l2_cadout_l[3] l2_cadout_l[10] l2_cadout_l[1] l2_cadout_l[8] vddio memdata[63] memdqs[16] memdata[120] memdata[60] memdata[55] memdata[115] memdqs[15] memdata[53] aj vdd l2_cadout_h[4] vss l2_cadout_h[3] vdd l2_cadout_h[1] vss vss memdata[58] memdata[62] vss memdata[61] memdata[50] vss memdata[54] ak l2_cadout_h[5] l2_clkout_l[0] l2_clkout_h[0] l2_cadout_l[2] l2_cadout_h[2] l2_cadout_l[0] l2_cadout_h[0] vddio memdata[59] memdqs[7] memdata[57] memdata[56] memdata[51] memdqs[6] al 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 24 connection diagrams chapter 4 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 chapter 5 pin designations 25 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 5 pin designations table 4, beginning on page 26, lists the pins alphabetically by pin name. 26 pin designations chapter 5 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 table 4. pin list by name clkin_h g16 l0_cadin_l[11] k4 l0_cadout_h[9] af5 clkin_l h16 l0_cadin_l[12] m4 l0_cadout_l[0] ae1 corefb_h l7 l0_cadin_l[13] p5 l0_cadout_l[1] ae3 corefb_l l6 l0_cadin_l[14] p4 l0_cadout_l[10] ad3 coresense_h k7 l0_cadin_l[15] t5 l0_cadout_l[11] ac5 dbrdy g8 l0_cadin_l[2] j2 l0_cadout_l[12] aa5 dbreq_l j7 l0_cadin_l[3] k1 l0_cadout_l[13] y3 fbclkout_h g18 l0_cadin_l[4] m1 l0_cadout_l[14] w5 fbclkout_l h18 l0_cadin_l[5] n2 l0_cadout_l[15] v3 l0_cadin_h[0] g3 l0_cadin_l[6] p1 l0_cadout_l[2] ac1 l0_cadin_h[1] g1 l0_cadin_l[7] r2 l0_cadout_l[3] ac3 l0_cadin_h[10] j5 l0_cadin_l[8] h5 l0_cadout_l[4] aa3 l0_cadin_h[11] k3 l0_cadin_l[9] h4 l0_cadout_l[5] w1 l0_cadin_h[12] m3 l0_cadout_h[0] af1 l0_cadout_l[6] w3 l0_cadin_h[13] n5 l0_cadout_h[1] ae2 l0_cadout_l[7] u1 l0_cadin_h[14] p3 l0_cadout_h[10] ad4 l0_cadout_l[8] af3 l0_cadin_h[15] r5 l0_cadout_h[11] ad5 l0_cadout_l[9] ae5 l0_cadin_h[2] j3 l0_cadout_h[12] ab5 l0_clkin_h[0] l3 l0_cadin_h[3] j1 l0_cadout_h[13] y4 l0_clkin_h[1] l5 l0_cadin_h[4] l1 l0_cadout_h[14] y5 l0_clkin_l[0] l2 l0_cadin_h[5] n3 l0_cadout_h[15] v4 l0_clkin_l[1] m5 l0_cadin_h[6] n1 l0_cadout_h[2] ad1 l0_clkout_h[0] ab1 l0_cadin_h[7] r3 l0_cadout_h[3] ac2 l0_clkout_h[1] ab4 l0_cadin_h[8] g5 l0_cadout_h[4] aa2 l0_clkout_l[0] aa1 l0_cadin_h[9] h3 l0_cadout_h[5] y1 l0_clkout_l[1] ab3 l0_cadin_l[0] g2 l0_cadout_h[6] w2 l0_ctlin_h[0] r1 l0_cadin_l[1] h1 l0_cadout_h[7] v1 l0_ctlin_l[0] t1 l0_cadin_l[10] k5 l0_cadout_h[8] af4 l0_ctlout_h[0] u2 chapter 5 pin designations 27 23932 rev 3.09 february 2004 amd opteron ? processor data sheet l0_ctlout_l[0] u3 l1_cadin_l[3] a19 l1_cadout_l[13] c9 l0_ref0 d1 l1_cadin_l[4] a17 l1_cadout_l[14] e10 l0_ref1 e1 l1_cadin_l[5] b16 l1_cadout_l[15] c11 l1_cadin_h[0] c22 l1_cadin_l[6] a15 l1_cadout_l[2] a6 l1_cadin_h[1] a22 l1_cadin_l[7] b14 l1_cadout_l[3] c6 l1_cadin_h[10] e20 l1_cadin_l[8] e21 l1_cadout_l[4] c8 l1_cadin_h[11] c19 l1_cadin_l[9] d21 l1_cadout_l[5] a10 l1_cadin_h[12] c17 l1_cadout_h[0] a3 l1_cadout_l[6] c10 l1_cadin_h[13] e16 l1_cadout_h[1] b4 l1_cadout_l[7] a12 l1_cadin_h[14] c15 l1_cadout_h[10] d5 l1_cadout_l[8] c3 l1_cadin_h[15] e14 l1_cadout_h[11] e5 l1_cadout_l[9] e4 l1_cadin_h[2] c20 l1_cadout_h[12] e7 l1_clkin_h[0] c18 l1_cadin_h[3] a20 l1_cadout_h[13] d9 l1_clkin_h[1] e18 l1_cadin_h[4] a18 l1_cadout_h[14] e9 l1_clkin_l[0] b18 l1_cadin_h[5] c16 l1_cadout_h[15] d11 l1_clkin_l[1] e17 l1_cadin_h[6] a16 l1_cadout_h[2] a5 l1_clkout_h[0] a7 l1_cadin_h[7] c14 l1_cadout_h[3] b6 l1_clkout_h[1] d7 l1_cadin_h[8] e22 l1_cadout_h[4] b8 l1_clkout_l[0] a8 l1_cadin_h[9] c21 l1_cadout_h[5] a9 l1_clkout_l[1] c7 l1_cadin_l[0] b22 l1_cadout_h[6] b10 l1_ctlin_h[0] a14 l1_cadin_l[1] a21 l1_cadout_h[7] a11 l1_ctlin_l[0] a13 l1_cadin_l[10] e19 l1_cadout_h[8] d3 l1_ctlout_h[0] b12 l1_cadin_l[11] d19 l1_cadout_h[9] e3 l1_ctlout_l[0] c12 l1_cadin_l[12] d17 l1_cadout_l[0] a4 l2_cadin_h[0] aj3 l1_cadin_l[13] e15 l1_cadout_l[1] c4 l2_cadin_h[1] al3 l1_cadin_l[14] d15 l1_cadout_l[10] c5 l2_cadin_h[10] ag5 l1_cadin_l[15] e13 l1_cadout_l[11] e6 l2_cadin_h[11] aj6 l1_cadin_l[2] b20 l1_cadout_l[12] e8 l2_cadin_h[12] aj8 table 4. pin list by name (continued) 28 pin designations chapter 5 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 l2_cadin_h[13] ag9 l2_cadout_h[1] ak21 l2_cadout_l[7] al13 l2_cadin_h[14] aj10 l2_cadout_h[10] ah20 l2_cadout_l[8] aj22 l2_cadin_h[15] ag11 l2_cadout_h[11] ag20 l2_cadout_l[9] ag21 l2_cadin_h[2] aj5 l2_cadout_h[12] ag18 l2_clkin_h[0] aj7 l2_cadin_h[3] al5 l2_cadout_h[13] ah16 l2_clkin_h[1] ag7 l2_cadin_h[4] al7 l2_cadout_h[14] ag16 l2_clkin_l[0] ak7 l2_cadin_h[5] aj9 l2_cadout_h[15] ah14 l2_clkin_l[1] ag8 l2_cadin_h[6] al9 l2_cadout_h[2] al20 l2_clkout_h[0] al18 l2_cadin_h[7] aj11 l2_cadout_h[3] ak19 l2_clkout_h[1] ah18 l2_cadin_h[8] ag3 l2_cadout_h[4] ak17 l2_clkout_l[0] al17 l2_cadin_h[9] aj4 l2_cadout_h[5] al16 l2_clkout_l[1] aj18 l2_cadin_l[0] ak3 l2_cadout_h[6] ak15 l2_ctlin_h[0] al11 l2_cadin_l[1] al4 l2_cadout_h[7] al14 l2_ctlin_l[0] al12 l2_cadin_l[10] ag6 l2_cadout_h[8] ah22 l2_ctlout_h[0] ak13 l2_cadin_l[11] ah6 l2_cadout_h[9] ag22 l2_ctlout_l[0] aj13 l2_cadin_l[12] ah8 l2_cadout_l[0] al21 ldtstop_l j6 l2_cadin_l[13] ag10 l2_cadout_l[1] aj21 memadd[0] v25 l2_cadin_l[14] ah10 l2_cadout_l[10] aj20 memadd[1] t25 l2_cadin_l[15] ag12 l2_cadout_l[11] ag19 memadd[10] v24 l2_cadin_l[2] ak5 l2_cadout_l[12] ag17 memadd[11] j25 l2_cadin_l[3] al6 l2_cadout_l[13] aj16 memadd[12] j24 l2_cadin_l[4] al8 l2_cadout_l[14] ag15 memadd[13] ae23 l2_cadin_l[5] ak9 l2_cadout_l[15] aj14 memadd[2] p23 l2_cadin_l[6] al10 l2_cadout_l[2] al19 memadd[3] n23 l2_cadin_l[7] ak11 l2_cadout_l[3] aj19 memadd[4] n25 l2_cadin_l[8] ag4 l2_cadout_l[4] aj17 memadd[5] m24 l2_cadin_l[9] ah4 l2_cadout_l[5] al15 memadd[6] m25 l2_cadout_h[0] al22 l2_cadout_l[6] aj15 memadd[7] k25 table 4. pin list by name (continued) chapter 5 pin designations 29 23932 rev 3.09 february 2004 amd opteron ? processor data sheet memadd[8] l23 memclk_lo_l[1] aa23 memdata[106] ac27 memadd[9] k23 memclk_lo_l[2] ad20 memdata[107] ad28 membank[0] w23 memclk_lo_l[3] j23 memdata[108] aa28 membank[1] w25 memclk_up_h[0] r23 memdata[109] aa26 memcas_l aa25 memclk_up_h[1] l24 memdata[11] e31 memcheck[0] r31 memclk_up_h[2] ae21 memdata[110] ac26 memcheck[1] r29 memclk_up_h[3] g20 memdata[111] ad27 memcheck[10] r26 memclk_up_l[0] t23 memdata[112] ad26 memcheck[11] t27 memclk_up_l[1] l25 memdata[113] ae27 memcheck[12] p25 memclk_up_l[2] ae20 memdata[114] ah29 memcheck[13] p24 memclk_up_l[3] g21 memdata[115] aj29 memcheck[14] t29 memcs_l[0] aa24 memdata[116] ae29 memcheck[15] u28 memcs_l[1] ab25 memdata[117] af28 memcheck[2] u30 memcs_l[2] ac25 memdata[118] af26 memcheck[3] v31 memcs_l[3] ac24 memdata[119] ag27 memcheck[4] p30 memcs_l[4] ad25 memdata[12] c28 memcheck[5] r30 memcs_l[5] ad24 memdata[120] aj26 memcheck[6] u29 memcs_l[6] ae25 memdata[121] af25 memcheck[7] v30 memcs_l[7] ad23 memdata[122] ah24 memcheck[8] r24 memdata[0] b24 memdata[123] af23 memcheck[9] r25 memdata[1] a25 memdata[124] ah27 memcke_lo h25 memdata[10] e30 memdata[125] ag26 memcke_up h24 memdata[100] u26 memdata[126] ah25 memclk_lo_h[0] u25 memdata[101] v28 memdata[127] ag24 memclk_lo_h[1] y23 memdata[102] y28 memdata[13] b30 memclk_lo_h[2] ad21 memdata[103] y27 memdata[14] c31 memclk_lo_h[3] h23 memdata[104] aa27 memdata[15] d31 memclk_lo_l[0] u24 memdata[105] ab29 memdata[16] f30 table 4. pin list by name (continued) 30 pin designations chapter 5 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 memdata[17] f31 memdata[42] af31 memdata[68] f23 memdata[18] h31 memdata[43] af29 memdata[69] d24 memdata[19] j31 memdata[44] ac30 memdata[7] b27 memdata[2] a27 memdata[45] ad31 memdata[70] e25 memdata[20] f29 memdata[46] af30 memdata[71] c26 memdata[21] g31 memdata[47] ag31 memdata[72] c27 memdata[22] j29 memdata[48] ag30 memdata[73] e27 memdata[23] j30 memdata[49] ah31 memdata[74] f28 memdata[24] k31 memdata[5] c24 memdata[75] g27 memdata[25] l31 memdata[50] ak28 memdata[76] d27 memdata[26] n31 memdata[51] al28 memdata[77] d29 memdata[27] p29 memdata[52] ag29 memdata[78] f26 memdata[28] l29 memdata[53] aj31 memdata[79] f27 memdata[29] l30 memdata[54] ak30 memdata[8] b28 memdata[3] a28 memdata[55] aj28 memdata[80] h26 memdata[30] m31 memdata[56] al27 memdata[81] h27 memdata[31] p31 memdata[57] al26 memdata[82] j28 memdata[32] v29 memdata[58] ak24 memdata[83] l26 memdata[33] y30 memdata[59] al24 memdata[84] g29 memdata[34] aa30 memdata[6] a26 memdata[85] h28 memdata[35] ac31 memdata[60] aj27 memdata[86] k27 memdata[36] w31 memdata[61] ak27 memdata[87] k29 memdata[37] y31 memdata[62] ak25 memdata[88] l27 memdata[38] aa29 memdata[63] aj24 memdata[89] m27 memdata[39] ab31 memdata[64] g23 memdata[9] a29 memdata[4] a24 memdata[65] e24 memdata[90] p26 memdata[40] ac29 memdata[66] f25 memdata[91] p27 memdata[41] ad30 memdata[67] e26 memdata[92] l28 table 4. pin list by name (continued) chapter 5 pin designations 31 23932 rev 3.09 february 2004 amd opteron ? processor data sheet memdata[93] m26 memdqs[28] e29 nc_ae14 ae14 memdata[94] n29 memdqs[29] j27 nc_ae9 ae9 memdata[95] p28 memdqs[3] m29 nc_af11 af11 memdata[96] u27 memdqs[30] n27 nc_af13 af13 memdata[97] v27 memdqs[31] w29 nc_af15 af15 memdata[98] w27 memdqs[32] ab27 nc_af9 af9 memdata[99] y26 memdqs[33] af27 nc_ag1 ag1 memdqs[0] c25 memdqs[34] ag25 nc_ag13 ag13 memdqs[1] c29 memdqs[35] r27 nc_ag14 ag14 memdqs[10] c30 memdqs[4] y29 nc_ah12 ah12 memdqs[11] h30 memdqs[5] ae31 nc_ah2 ah2 memdqs[12] m30 memdqs[6] al29 nc_aj12 aj12 memdqs[13] aa31 memdqs[7] al25 nc_aj2 aj2 memdqs[14] ad29 memdqs[8] t31 nc_c13 c13 memdqs[15] aj30 memdqs[9] b25 nc_d13 d13 memdqs[16] aj25 memras_l y25 nc_e11 e11 memdqs[17] u31 memreset_l g25 nc_e12 e12 memdqs[18] d25 memvref0 f22 nc_f7 f7 memdqs[19] e28 memvref1 af22 nc_g14 g14 memdqs[2] h29 memwe_l y24 nc_g6 g6 memdqs[20] j26 memzn af17 nc_h12 h12 memdqs[21] m28 memzp ae16 nc_h13 h13 memdqs[22] v26 nc_aa6 aa6 nc_h14 h14 memdqs[23] ac28 nc_ac6 ac6 nc_h7 h7 memdqs[24] ag28 nc_ae10 ae10 nc_h9 h9 memdqs[25] af24 nc_ae11 ae11 nc_k8 k8 memdqs[26] r28 nc_ae12 ae12 nc_l8 l8 memdqs[27] f24 nc_ae13 ae13 nc_m23 m23 table 4. pin list by name (continued) 32 pin designations chapter 5 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 nc_n6 n6 vdd d12 vdd n9 nc_r6 r6 vdd d16 vdd n11 nc_t3 t3 vdd d20 vdd n13 nc_t4 t4 vdd f6 vdd n15 nc_t7 t7 vdd f11 vdd n17 nc_u5 u5 vdd f15 vdd n19 nc_u6 u6 vdd f18 vdd p6 nc_v23 v23 vdd f19 vdd p10 nc_v5 v5 vdd g7 vdd p12 nc_w6 w6 vdd h2 vdd p14 presence_det ak2 vdd j4 vdd p16 pwrok f12 vdd j13 vdd p18 reset_l g12 vdd k6 vdd p20 tck ae7 vdd k12 vdd r9 tdi af7 vdd k18 vdd r11 tdo ae8 vdd l9 vdd r13 thermda aj1 vdd l11 vdd r15 thermdc ah1 vdd l13 vdd r17 thermtrip_l ae15 vdd l15 vdd r19 tms ae6 vdd l17 vdd t2 trst_l ad7 vdd m2 vdd t8 vdd b5 vdd m10 vdd t10 vdd b9 vdd m12 vdd t12 vdd b13 vdd m14 vdd t14 vdd b17 vdd m16 vdd t16 vdd b21 vdd m18 vdd t18 vdd d4 vdd m20 vdd t20 vdd d8 vdd n4 vdd u4 table 4. pin list by name (continued) chapter 5 pin designations 33 23932 rev 3.09 february 2004 amd opteron ? processor data sheet vdd u9 vdd aa11 vdda2 d2 vdd u11 vdd aa13 vdda3 c2 vdd u13 vdd aa15 vddio a23 vdd u15 vdd aa17 vddio c23 vdd u17 vdd ab6 vddio d26 vdd u19 vdd ab8 vddio d28 vdd v6 vdd ab12 vddio e23 vdd v10 vdd ab18 vddio g26 vdd v12 vdd ac13 vddio g28 vdd v14 vdd ad2 vddio h22 vdd v16 vdd ad12 vddio j21 vdd v18 vdd ad14 vddio k20 vdd v20 vdd ad16 vddio k22 vdd w9 vdd ae4 vddio k26 vdd w11 vdd af6 vddio k28 vdd w13 vdd af10 vddio l19 vdd w15 vdd af14 vddio l21 vdd w17 vdd ah5 vddio m22 vdd w19 vdd ah9 vddio n21 vdd y2 vdd ah13 vddio n26 vdd y10 vdd ah17 vddio n28 vdd y12 vdd ah21 vddio p22 vdd y14 vdd ak4 vddio r21 vdd y16 vdd ak8 vddio t22 vdd y18 vdd ak12 vddio t26 vdd y20 vdd ak16 vddio t28 vdd aa4 vdd ak20 vddio u21 vdd aa9 vdda1 c1 vddio u23 table 4. pin list by name (continued) 34 pin designations chapter 5 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 vddio v22 vldt_0 m8 vss b7 vddio w21 vldt_0 n7 vss b11 vddio w26 vldt_0 p8 vss b15 vddio w28 vldt_0 r7 vss b19 vddio y22 vldt_0 u7 vss b23 vddio aa19 vldt_0 v8 vss b26 vddio aa21 vldt_0 w7 vss b29 vddio ab20 vldt_0 y8 vss d6 vddio ab22 vldt_0 aa7 vss d10 vddio ab26 vldt_1 h8 vss d14 vddio ab28 vldt_1 h10 vss d18 vddio ac21 vldt_1 j9 vss d22 vddio ad22 vldt_1 j11 vss d23 vddio ae26 vldt_1 j15 vss d30 vddio ae28 vldt_1 j16 vss e2 vddio ag23 vldt_1 k10 vss f1 vddio ah26 vldt_1 k14 vss f2 vddio ah28 vldt_1 k16 vss f5 vddio aj23 vldt_2 ab10 vss f8 vddio al23 vldt_2 ab14 vss f10 vddio_sense af20 vldt_2 ab16 vss f13 vddiofb_h ab23 vldt_2 ac9 vss f14 vddiofb_l ac23 vldt_2 ac11 vss f16 vid[0] g11 vldt_2 ac15 vss f17 vid[1] h11 vldt_2 ac16 vss g4 vid[2] g10 vldt_2 ad8 vss g13 vid[3] f9 vldt_2 ad10 vss g15 vid[4] g9 vss b3 vss g17 table 4. pin list by name (continued) chapter 5 pin designations 35 23932 rev 3.09 february 2004 amd opteron ? processor data sheet vss g22 vss l16 vss p15 vss g24 vss l18 vss p17 vss g30 vss l20 vss p19 vss h6 vss l22 vss p21 vss h15 vss m6 vss r4 vss h17 vss m7 vss r8 vss j8 vss m9 vss r10 vss j10 vss m11 vss r12 vss j12 vss m13 vss r14 vss j14 vss m15 vss r16 vss j17 vss m17 vss r18 vss j18 vss m19 vss r20 vss j20 vss m21 vss r22 vss j22 vss n8 vss t6 vss k2 vss n10 vss t9 vss k9 vss n12 vss t11 vss k11 vss n14 vss t13 vss k13 vss n16 vss t15 vss k15 vss n18 vss t17 vss k17 vss n20 vss t19 vss k19 vss n22 vss t21 vss k21 vss n24 vss t24 vss k24 vss n30 vss t30 vss k30 vss p2 vss u8 vss l4 vss p7 vss u10 vss l10 vss p9 vss u12 vss l12 vss p11 vss u14 vss l14 vss p13 vss u16 table 4. pin list by name (continued) 36 pin designations chapter 5 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 vss u18 vss y15 vss ac20 vss u20 vss y17 vss ac22 vss u22 vss y19 vss ad6 vss v2 vss y21 vss ad9 vss v7 vss aa8 vss ad11 vss v9 vss aa10 vss ad13 vss v11 vss aa12 vss ad15 vss v13 vss aa14 vss ad17 vss v15 vss aa16 vss ae17 vss v17 vss aa18 vss ae22 vss v19 vss aa20 vss ae24 vss v21 vss aa22 vss ae30 vss w4 vss ab2 vss af2 vss w8 vss ab7 vss af8 vss w10 vss ab9 vss af12 vss w12 vss ab11 vss af16 vss w14 vss ab13 vss af21 vss w16 vss ab15 vss ag2 vss w18 vss ab17 vss ah3 vss w20 vss ab19 vss ah7 vss w22 vss ab21 vss ah11 vss w24 vss ab24 vss ah15 vss w30 vss ab30 vss ah19 vss y6 vss ac4 vss ah23 vss y7 vss ac10 vss ah30 vss y9 vss ac12 vss ak6 vss y11 vss ac14 vss ak10 vss y13 vss ac17 vss ak14 table 4. pin list by name (continued) chapter 5 pin designations 37 23932 rev 3.09 february 2004 amd opteron ? processor data sheet vss ak18 vss ak22 vss ak23 vss ak26 vss ak29 vtt af18 vtt f20 vtt f21 vtt g19 vtt h19 vtt j19 vtt ac18 vtt ac19 vtt ae18 vtt ae19 vtt_sense af19 table 4. pin list by name (continued) 38 pin designations chapter 5 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 chapter 6 pin descriptions 39 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 6 pin descriptions table 5 describes the terms used in the pin description tables found in this chapter. the pins are organized within the following functional groups: hypertransport ? technology interface ddr sdram memory interface miscellaneous pins, including clock, jtag, and debug pins all pins are described in the tables beginning on page 40. table 5. pin description table definitions notes: 1. refer to table 33, ? combined ac and dc operating conditions for power supplies, ? on page 72 for vddio voltage specifications. pin types applicable section in electrical chapter i-ht input, hypertransport ? technology, differential ? hypertransport ? technology interface ? on page 48 o-ht output, hypertransport technology, differential ? hypertransport ? technology interface ? on page 48 b-ios bidirectional, vddio 1 single-ended ? ddr sdram and miscellaneous pins ? on page 51 i-ios input, vddio 1 , single-ended ? ddr sdram and miscellaneous pins ? on page 51 i-iod input, vddio 1 , differential ? clock pins ? on page 63 o-iod output, vddio 1 , differential ? clock pins ? on page 63 o-ios output, vddio 1 , single-ended ? ddr sdram and miscellaneous pins ? on page 51 o-io-od output, vddio 1 , open drain ? ddr sdram and miscellaneous pins ? on page 51 aanalog ? power supplies ? on page 72 s supply voltage ? power supplies ? on page 72 vref voltage reference ? ddr sdram and miscellaneous pins ? on page 51 40 pin descriptions chapter 6 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 6.1 hypertransport ? technology pins notes: 1. these pins are used in an alternating fashion to compensate r tt by internal comparison to 3/4 vldt and 1/4 vldt and compensate r on by comparison to each other around 1/2 vldt. for proper resistor value, see the amd athlon ? 64 fx and amd opteron ? processor motherboard design guide , order# 25180. table 6. hypertransport ? technology pin descriptions signal name type description l0_clkin_h/l[1:0] i-ht link 0 clock input l0_ctlin_h/l[0] i-ht link 0 control input l0_cadin_h/l[15:0] i-ht link 0 command/address/data input l0_clkout_h/l[1:0] o-ht link 0 clock outputs l0_ctlout_h/l[0] o-ht link 0 control output l0_cadout_h/l[15:0] o-ht link 0 command/address/data outputs l1_clkin_h/l[1:0] i-ht link 1 clock input l1_ctlin_h/l[0] i-ht link 1 control input l1_cadin_h/l[15:0] i-ht link 1 command/address/data input l1_clkout_h/l[1:0] o-ht link 1 clock outputs l1_ctlout_h/l[0] o-ht link 1 control output l1_cadout_h/l[15:0] o-ht link 1 command/address/data outputs l2_clkin_h/l[1:0] i-ht link 2 clock input l2_ctlin_h/l[0] i-ht link 2 control input l2_cadin[15:0] i-ht link 2 command/address/data input l2_clkout_h/l[1:0] o-ht link 2 clock outputs l2_ctlout_h/l[0] o-ht link 2 control output l2_cadout_h/l[15:0] o-ht link 2 command/address/data outputs l0_ref1 a compensation resistor to vldt 1 l0_ref0 a compensation resistor to vss 1 chapter 6 pin descriptions 41 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 6.2 ddr sdram memory interface pins table 7. ddr sdram memory interface pin descriptions signal name type description memclk_up_h/l[3] o-iod dram clock connected to dimm3 for the upper half of the data bus memclk_up_h/l[2] o-iod dram clock connected to dimm2 for the upper half of the data bus memclk_up_h/l[1] o-iod dram clock connected to dimm1 for the upper half of the data bus memclk_up_h/l[0] o-iod dram clock connected to dimm0 for the upper half of the data bus memclk_lo_h/l[3] o-iod dram clock connected to dimm3 for the lower half of the data bus memclk_lo_h/l[2] o-iod dram clock connected to dimm2 for the lower half of the data bus memclk_lo_h/l[1] o-iod dram clock connected to dimm1 for the lower half of the data bus memclk_lo_h/l[0] o-iod dram clock connected to dimm0 for the lower half of the data bus memcke_up o-ios dram clock enable memcke_lo o-ios dram clock enable memdqs[35] b-ios dram data strobe synchronous with memcheck[15:12] for x4 dimms. memdqs[34:27] b-ios dram data strobe synchronous with the high-order nibbles of memdata[127:64] for x4 dimms memdqs[26] b-ios dram data strobe synchronous with memcheck[11:8] for x4 dimms and memcheck[15:8] for x8/x16 dimms. memdqs[25:18] b-ios dram data strobe synchronous with the low-order nibbles of memdata[127:64] for x4 dimms and all nibbles for x8/x16 dimms memdqs[17] b-ios dram data strobe synchronous with memcheck[7:4] for x4 dimms memdqs[16:9] b-ios dram data strobe synchronous with high-order nibbles of memdata[63:0] for x4 dimms memdqs[8] b-ios dram data strobe synchronous with memcheck[3:0] for x4 dimms and memcheck[7:0] for x8/x16 dimms memdqs[7:0] b-ios dram data strobe synchronous with low-order nibbles of memdata[127:64] for x4 dimms and all nibbles for x8/x16 dimms memdata[127:0] b-ios dram interface data bus memcheck[15:0] b-ios dram interface ecc check bits memcs_l[7:0] o-ios dram chip selects 1 memras_l o-ios dram row address select memcas_l o-ios dram column address select 42 pin descriptions chapter 6 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 notes: 1. for connection details and proper resistor values, see the amd athlon ? 64 fx and amd opteron ? processor motherboard design guide , order# 25180. memwe_l o-ios dram write enable memadd[13:0] o-ios dram column/row address membank[1:0] o-ios dram bank address memreset_l o-ios dram reset pin for suspend-to-ram power management mode. this pin is required for registered dimms only. memvref vref dram interface voltage reference 1 memzp a compensation resistor tied to vss 1 memzn a compensation resistor tied to 2.5 v 1 table 7. ddr sdram memory interface pin descriptions (continued) signal name type description chapter 6 pin descriptions 43 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 6.3 miscellaneous pins table 8. clock pin descriptions signal name type description clkin_h/l i-iod 200-mhz pll reference clock fbclkout_h/l o-iod core clock pll 200-mhz feedback clock table 9. miscellaneous pin descriptions signal name type description reset_l i-ios system reset pwrok i-ios indicates that voltages and clocks have reached specified operation ldtstop_l i-ios hypertransport ? technology stop control input. used for power management and for changing hypertransport link width and frequency. vid[4:0] o-ios voltage id to the regulator thermda a anode (+) of the thermal diode thermdc a cathode ( ? ) of the thermal diode thermtrip_l o-io-od thermal sensor trip output, asserted at nominal temperature of 125 o c. corefb_h/l a differential feedback for vdd power supply vddiofb_h/l a differential feedback for vddio power supply core_sense a vdd voltage monitor pin vdda s filtered pll supply voltage vtt_sense a vtt voltage monitor pin vddio_sense a vddio voltage monitor pin vdd s core power supply vddio s ddr sdram i/o ring power supply vldt_0 vldt_1 vldt_2 s hypertransport ? i/o ring power supply vtt s vtt regulator voltage 44 pin descriptions chapter 6 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 presence_det s this pin can be connected to vss or used for detection of the processor in multiprocessor configurations. when used as a presence detection bit it should be pulled up and sensed via the circuitry that is used to detect installed processors on the motherboard. this pin is connected to vss internally. vss s ground table 10. vid[4:0] encoding vid[4:0] vdd vid[4:0] vdd vid[4:0] vdd vid[4:0] vdd 0x00000 1.550 v 0x01000 1.350 v 0x10000 1.150 v 0x11000 0.950 v 0x00001 1.525 v 0x01001 1.325 v 0x10001 1.125 v 0x11001 0.925 v 0x00010 1.500 v 0x01010 1.300 v 0x10010 1.100 v 0x11010 0.900 v 0x00011 1.475 v 0x01011 1.275 v 0x10011 1.075 v 0x11011 0.875 v 0x00100 1.450 v 0x01100 1.250 v 0x10100 1.050 v 0x11100 0.850 v 0x00101 1.425 v 0x01101 1.225 v 0x10101 1.025 v 0x11101 0.825 v 0x00110 1.400 v 0x01110 1.200 v 0x10110 1.000 v 0x11110 0.800 v 0x00111 1.375 v 0x01111 1. 175 v 0x10111 0.975 v 0x1 1111 off table 11. jtag pin descriptions signal name type description tck i-ios jtag clock tms i-ios jtag mode select trst_l i-ios jtag reset tdi i-ios jtag data input tdo o-ios jtag data output table 9. miscellaneous pin descriptions (continued) signal name type description chapter 6 pin descriptions 45 23932 rev 3.09 february 2004 amd opteron ? processor data sheet table 12. debug pin descriptions signal name type description dbreq_l i-ios debug request dbrdy o-ios debug ready 46 pin descriptions chapter 6 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 6.4 pin states at reset the default pin states are listed below. these are listed for all output and bidirectional pins in the power-on reset state (reset) as well as the acpi s1 and s3 power management states. for differential inputs, ? 0 ? and ? 1 ? refer to the high-end differential output. low-end differential outputs are inverted. definitions of pin states: x: either logic 1 or 0, z: tristated, t: toggling between 0 and 1 table 13. reset pin state pin name reset state s1 state s3 state comments l*_clkout* t z z tristated in s1 only if programmed to do so. l*_ctlout* 0 z z tristated in s1 only if programmed to do so. l*_cadout* 1 z z tristated in s1 only if programmed to do so. memclk* z z z memdqs* z z z memcke* 0 0 0 in s3, memcke* is forced to a logic low. memdata* z z z memcheck* z z z memcs_l* 1 z z memras_l 1 z z memcas_l 1 z z memwe_l 1 z z memadd* 0 z z membank* 0 z z memreset_l 0 0 0 in s3, memreset_l is forced to logic 0. memzn 1 1 1 memzp 0 0 0 fbclkout* t t z tdo x x z dbrdy 0 0 z vid[4:0] x x x thermtrip_l z x z chapter 7 electrical data 47 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 7 electrical data 7.1 absolute maximum ratings stresses greater than those listed in table 14 may cause permanent damage to the device and motherboard. systems using this device must be designed to ensure that these parameters are not violated. violation of these ratings will void the product warranty. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer to amd opteron tm processor power and thermal data sheet, order# 30417, for maximum case temperature specifications. table 14. absolute maximum ratings for amd opteron ? processor characteristic range storage temperature ? 55 o c to 85 o c vldt supply voltage relative to vss ? 0.3 v to 1.5 v vdd supply voltage relative to vss ? 0.3 v to 1.65 v vtt supply voltage relative to vss ? 0.3 v to 1.65 v vddio supply voltage relative to vss ? 1 v to 2.9 v vdda supply voltage relative to vss ? 0.3 v to 3.0 v memvref input voltage relative to vss ? 1 v to 2.9 v input voltage relative to vss for hypertransport ? technology interface ? 0.3 v to 1.5 v differential input voltage for hypertransport ? technology interface ? 1.5 v to 1.5 v input voltage relative to vss for ddr sdram memory interface and miscellaneous pins ? 1 v to 2.9v 48 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 7.2 hypertransport ? technology interface 7.2.1 operating conditions notes: 1. measured by comparing each signal voltage with respect to ground. 2. measured at <100 mhz, considered slow enough to attain both 0 and 1 logic state voltage levels without ac transients on signals and supplies. table 15. dc operating conditions for hypertransport ? technology interface symbol parameter unit min typ max notes v od output differential voltage mv 495 600 715 1, 2 v ocm output common mode voltage mv 495 600 715 1, 2 v id input differential voltage mv 200 600 1000 1, 2 v icm input common mode voltage mv 440 600 780 1, 2 deltav od change in v od from 0 to 1 state mv ? 15 0 15 1 deltav ocm change in v ocm from 0 to 1 state mv ? 15 0 15 1 deltav id change in v id from 0 to 1 state mv ? 15 0 15 1 deltav icm change in v icm from 0 to 1 state mv ? 15 0 15 1 i l input leakage current ma ? 11 i oz output tristate leakage current ma ? 11 r on output driver impedance ohm 45 50 55 deltar on change in r on driving 0=>1 or 1=>0 % ? 2.5 0 2.5 r tt input differential impedance ohm 90 100 110 chapter 7 electrical data 49 23932 rev 3.09 february 2004 amd opteron ? processor data sheet notes: 1. measured by comparing each signal voltage with respect to ground. 2. measured in a differential fashion relative to the complement signal. 3. measured from crossing points of differential pairs. 4. input setup and hold times are measured from the crossing point of cad versus the crossing point of clk, effectively including the edge time to achieve vid min ac. table 16. ac operating conditions for hypertransport ? technology interface symbol parameter unit min typ max notes v od output differential voltage mv 400 820 1 v ocm output common mode voltage mv 440 780 1 v id input differential voltage mv 300 900 1 v icm input common mode voltage mv 385 845 1 deltav od change in v od from 0 to 1 state mv ? 75 75 1 deltav ocm change in v ocm from 0 to 1 state mv ? 50 50 1 deltav id change in v id from 0 to 1 state mv ? 125 125 1 deltav icm change in v icm from 0 to 1 state mv ? 100 100 1 t rise input rising edge rate v/ns 1 4 1, 2 t fall input falling edge rate v/ns 1 4 1, 2 c in input pad capacitance pf 2 c out output pad capacitance pf 3 c delta c in pad capacitance range across group pf 0.5 t cadv output cad valid ps 166 459 3 tpherr accumulated phase error, clkin_h/l to l*_clkout_h/l[1:0] ps 0 5000 t su device setup time ps 110 3, 4 t hld device hold time ps 110 3, 4 r tt input differential impedance ohm 90 100 110 r on output impedance ohm 45 50 55 deltar on change in r on driving 0=>1 or 1=>0 % ? 2.5 2.5 50 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 7.2.2 reference information table 17. internal termination for hypertransport ? technology interface pin internal termination value tolerance l*_cadin* differential r tt 100 ohm (pvt-compensated) 10% l*_ctlin* differential r tt 100 ohm (pvt-compensated) 10% l*_clkin* differential r tt 100 ohm (pvt-compensated) 10% chapter 7 electrical data 51 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 7.3 ddr sdram and miscellaneous pins this section includes electrical specifications for all ddr sdram pins described in ? ddr sdram memory interface pins ? on page 41, and the thermtrip_l , reset_l , ldtstop_l , pwrok , vid[4:0] , tck , tms , trst_l , tdi , tdo , dbreq_l , and dbrdy pins described in ? miscellaneous pins ? on page 43. 52 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 7.3.1 operating conditions notes: the notes for table 18 through table 21 appear on page 54. table 18. dc operating conditions symbol parameters unit min typ max notes v ref reference voltage (for i/o), memvref pin v 0.49*v ddio_dc min 0.5*v ddio_dc 0.51*v ddio_dc max 1, 12 i l input leakage current any input: 0 < v in < v ddio v (all other pins not under test = 0v) ma -1 1 i oz output leakage current any output: 0 < v out < v ddio v ma -1 1 v ih input high voltage (logic 1) v v ref + 0.15 - - 2 v il input low voltage (logic 0) v - - v ref - 0.15 2 v oh output high voltage (logic 1) (for vid[4:0]) v2.0 output high voltage (logic 1) (for all other pins) v1.8 v ol output low voltage (logic 0) v 0.65 i oh output levels -output high cur- rent (v out = v ddio /2) ma -25 -28 -33 3 i ol output levels - output low cur- rent (v out =v ddio /2) ma 25 28 32 3 v od differential output voltage (for ck & ck ) v 1.2 1.3 1.4 4 v od change in v od magnitude mv -100 - 100 5 v ocm output common mode voltage (for ck & ck ) v 1.1 1.25 1.4 6 v ocm change in v ocm magnitude mv -100 - 100 7 ? ? chapter 7 electrical data 53 23932 rev 3.09 february 2004 amd opteron ? processor data sheet table 19. ac operating conditions symbol parameters unit min typ max notes v ref reference voltage (for i/o), memvref pin vv ref (dc) - 2% v ref (dc) + 2% 1 v ih input high voltage (logic 1) v v ref + 0.35 - 2 v il input low voltage (logic 0) v - v ref - 0.35 2 v od differential output voltage (for ck & ck ) v 1.0 1.3 1.6 4 v od change in v od magnitude mv -150 - 150 5 v ocm output common mode voltage (for ck & ck ) v 0.9 1.25 1.6 6 v ocm change in v ocm magnitude mv -200 - 200 7 table 20. input capacitance symbol parameters unit min typ max notes c in input capacitance (dq & dqs) pf 3.0 3.5 4.0 c delta input capacitance pf - - 0.4 8 table 21. slew rate of ddr sdram signals symbol parameters unit min typ max notes s out output slew rate (pullup and pull- down) v/ns 2 3 4 9 s out_rat io output slew rate ratio between pullup and pulldown 0.75 1 1.25 10 s in input slew rate v/ns 0.5 4 11 ? ? ? 54 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 1. v ref is expected to be equal to 0.5*v ddio and to track variations in the dc level of the same. peak to peak noise on v ref may not exceed + 2% of the dc value. 2. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. the receiver effectively switches to the new logic state when receiver input crosses the ac level. the new logic state is maintained as long as the input stays beyond the dc threshold. 3. with compensation the granularity between nmos current and pmos current cannot exceed 3ma. the range is 6ma due to 10% variation. 4. v od is the differential output voltage or the voltage difference between true and complement under dc or ac conditions. 5. v od is the change in magnitude between the differential output voltage while driving a logic 0 and while driving a logic 1. 6. v ocm is the output common mode voltage defined as the average of the true voltage magnitude and the complement voltage magnitude relative to ground under dc or ac conditions. 7. v ocm is the change in magnitude between the output common mode voltage while driving a logic 0 and while driving a logic 1. 8. c means the difference in capacitance between any memdata/memdqs pin to any other memdata/memdqs pin. 9. pullup and pulldown slew rate is measured into r tt (50 ohms) to v tt as shown in figure 4. the slew rate is measured between v ref + 300 mv. it is designed for any pattern of data, including all outputs switching and only one output switching. 10. the ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 11. the slew rate is measured at the cpu pin between v ref + 150 mv. minimum and maximum input slew rate specification is set based on dram output slew rate specification. 12. vddio_dc is defined in table 33 on page 72. figure 4. slew rate measurement example ? ? ? r tt v tt 0 pf driver chapter 7 electrical data 55 23932 rev 3.09 february 2004 amd opteron ? processor data sheet table 22. package routing skew routing measurement skew (ps) any memclk clock pair to any other memclk clock pair + 100 any memclk pair to any memdqs pair + 100 any memdqs pair to any memdata associated within pair + 75 any memclk pair to any memadd/cmd + 100 pad skew + 250 56 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 7.3.2 ac operating characteristics 1. write cycle timing parameter 2. the skew consists of pad output skew (+ 250ps) and package routing skew between any two clock pairs (+ 100ps). 3. tcks timing parameter, refer to figure 5 on page 58. 4. the timing consists of pad output skew (+ 250ps) and package routing skew between any memclk to any memdqs (+ 100ps). 5. tdqs timing parameter, refer to figure 6 on page 58. 6. the skew consists of pad output skew (+ 250ps) and package routing skew between any memclk to any memdqs (+ 100ps). minimum dqs pulse width is 45% of memclk. 7. tdss, tdsh timing parameters, refer to figure 7 on page 59. 8. during write, dq signals are driven quarter clock earlier such that dqs is placed in the center of data eye window. the skew consists of pad output skew (+ 250ps), package routing skew between any dqs signals and it ? s associated dq signals (+ 75ps) and maximum clock granularity (+ 312.5 ps). table 23. electrical ac timing characteristics for ddr sdram signals symbol parameters unit min typ max notes tck memclk cycle time ps 5000 - 10000 15 tch memclk high pulse width ps 0.45*tck - 0.55*tck tcl memclk low pulse width ps 0.45*tck - 0.55*tck tcks memclk output skew ps -350 - 350 1,2,3 tdqsh memdqs high pulse width ps 0.45*tck - 0.55*tck 1 tdqsl memdqs low pulse width ps 0.45*tck - 0.55*tck 1 tdqs memclk to memdqs ps -350 - 350 1,4,5 tdss memdqs falling edge to mem- clk rising edge ps 0.45*tck - 350 - - 1,6,7 tdsh memclk rising edge to mem- dqs falling edge ps 0.45*tck - 350 - - 1,6,7 tdqsqv memdqs to memdata shift (when data becomes valid) ps -{0.5* tdqshmax - [638]} - -{0.5* tdqshmin + [638]} 1,8,9 tdqsqiv memdqs to memdata shift (when data becomes invalid) ps {0.5*tdqsh- min - [638]} - {0.5* tdqshmax + [638]} 1,8,9 t2 memadd/cmd to memclk (registered dimm environment - memadd/cmd are launched 1/2 clock early) ps - 350 - 350 1,10,11 t3 memdata edge arrival relative to memdqs ps -{tck/4 - [350+0.2* (tck/4)]} -tck/4 - [350+0.2* (tck/4)] 12,13,14 chapter 7 electrical data 57 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 9. tdqsqv and tdqsqiv timing parameters apply only within dqs and its associated dq signals. refer to figure 8 on page 60. 10. the skew consists of pad output skew (+ 250 ps) and package routing skew (+ 100 ps) between any memclk pair to any memadd/cmd signal. maximum clock granularity skew is 312.5 ps. 11. t2 timing parameter, applies to registered dimm environment only - memadd/cmd signals are launched 1/2 clock cycle early. the granularity term does not apply here. refer to figure 9 on page 61. 12. read cycle timing parameter. 13. the pdl placement uncertainty is 20%. package skew between dqs and its associated dqs is 75ps. the sum of setup/hold time & receiver uncertainty is 275ps. 14. t3 timing parameter, refer to figure 10 on page 62. 15. the slow operation of 10ns cycle time is specifically included for functional test purpose only. all electrical characterization will be performed at full speed however all functional tests will be performed at 10ns cycle time. 58 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 figure 5. memclk output skew figure 6. memdqs timing parameter ck ck ck ck ck ck tck tcks min tcks max ck ck tck tdqs min tdqs max dqs dqs chapter 7 electrical data 59 23932 rev 3.09 february 2004 amd opteron ? processor data sheet t figure 7. dss/tdsh timing parameters ck ck tck tdsh min tdss min dqs dqs 60 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 figure 8. tdqsqv/tdqsqiv timing parameters ck ck tck dqs dqs ideal 90 o phase shift - tdqsqv typical tdqsqv max - earliest time data can become valid tdqsqv min - latest time data can become valid dqs dqs dqs ideal 90 o phase shift - tdqsqiv typical tdqsqiv min - earliest time data can become in-valid tdqsqiv max - latest time data can become invalid dqs dqs chapter 7 electrical data 61 23932 rev 3.09 february 2004 amd opteron ? processor data sheet figure 9. memadd/cmd to memclk timing parameter (registered dimms) ck ck tck t2 =0 (ideal timing) addr/cmd addr/cmd addr/cmd tck/2 t2 max = 350 t2 max t2 min tck/2 t2 min = -350 62 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 figure 10.memdqs edge arrival relative to dqs dqs dqs perfect edge aligned t3 = 0 ps dqs late arrival from strobe t3 max dqs early arrival from strobe t3 min t3 max t3 min setup package + pdl + receiver uncertainty chapter 7 electrical data 63 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 7.4 clock pins 7.4.1 operating conditions notes: 1. v od is the differential output voltage or the voltage difference between true and complement under dc or ac conditions. 2. deltav od is the change in magnitude between the differential output voltage while driving logic 0 and while driving logic 1. 3. v ocm is the output common mode voltage defined as the average of the true voltage magnitude and the complement voltage relative to ground under dc or ac conditions. 4. deltav ocm is the change in magnitude between the output common mode voltage while driving logic 0 and while driving logic 1 under dc or ac conditions. table 24. dc operating conditions for clkin_h/l and fbclkout_h/l pins symbol parameters unit min typ max notes v id differential input voltage mv 300 2400 deltav id change in v id magnitude mv ? 50 50 v icm input common mode voltage mv vtt ? 100 vtt vtt+100 deltav icm change in v icm magnitude mv ? 50 50 v od differential output voltage v 1.2 1.3 1.4 1 deltav od change in v od magnitude mv ? 50 50 2 v ocm output common mode voltage v 1.1 1.25 1.4 3 deltav ocm change in v ocm magnitude mv ? 50 50 4 64 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 notes: 1. v od is the differential output voltage or the voltage difference between true and complement under dc or ac conditions. 2. delta v od is the change in magnitude between the differential output voltage while driving logic 0 and while driving logic 1. 3. v ocm is the output common mode voltage defined as the average of the true voltage magnitude and the complement voltage relative to ground under dc or ac conditions. 4. delta v ocm is the change in magnitude between the output common mode voltage while driving logic 0 and while driving logic 1 under dc or ac conditions. 5. measured differentially through the range of vicm ? 400 mv to vicm + 400 mv. 6. spread spectrum clocking is limited to ? 0.5% downspread under normal operation. 7. measured at the differential crossing point. maximum difference of cycle time between two adjacent cycles. table 25. ac operating conditions for clkin_h/l and fbclkout_h/l pins symbol parameter unit min typ max notes f (pll mode, vdda=2.5 v) input frequency range (ssc) mhz 198.8 200 6 t jc jitter, cycle-to-cycle ps 0 200 7 dc input duty cycle (clkin_h/l) % 30 70 v bias input bias voltage node mv vtt vtt vtt v id differential input voltage mv 400 2300 deltav id change in v id magnitude mv ? 150 150 v icm input common mode voltage mv v bias ? 200 v bias +200 deltav icm change in v icm magnitude mv ? 200 200 v od differential output voltage v 1.2 1.3 1.4 1 deltav od change in v od magnitude mv ? 100 100 2 v ocm output common mode voltage v 1.1 1.25 1.4 3 deltav ocm change in v ocm magnitude mv ? 100 100 4 i f input falling edge rate v/ns 1.2 10 5 i r input rising edge rate v/ns 1.2 10 5 c in input capacitance pf 0 5 chapter 7 electrical data 65 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 7.5 power-up signal sequencing figure 12 on page 67 illustrates the signal sequencing requirements during a cold reset (power-up conditions). the hypertransport tm link reset sequencing is defined in the hypertransport ? i/o link specification . the following list describes the power-up signal sequencing illustrated in figure 12. note that the numbered items correspond to the numbers in figure 12. 1. reset_l must be asserted a minimum of 1ms prior to the assertion of pwrok, as defined in the hypertransport ? i/o link specification . the tms pin must be asserted a minimum of 10ns before pwrok assertion and must be held in the high state a minimum of 10ns after the assertion of pwrok. 2. clkin_h/l must be within specification at the time the vdd power supply begins to ramp. 3. pwrok remains deasserted at least 1ms after clkin_h/l is stable and voltages to the processor are within specification. the processor determines if there are devices attached to its hypertransport links 10 s after the assertion of pwrok. 4. after pwrok assertion, the vid[4:0] signals change from the default code (01110b = 1.2 v) to the value programmed during device manufacturing. the pll begins locking to the frequency programmed during device manufacturing 160 s after pwrok is asserted. 5. ldtstop_l must be deasserted a minimum of 1 s before the deassertion of reset_l, as defined by the hypertransport ? i/o link specification . 6. the reset_l signal remains asserted a minimum of 1ms after pwrok assertion, as defined in the hypertransport ? i/o link specification . the clocks from the transmitters of all hypertransport technology devices must be stable before reset_l is deasserted. 7. the memclk_lo_h/l[3:0] and memclk_up_h/l[3:0] signals are stable after bios sets the memory clock ratio valid (mcr) bit in the processor ? s dram config upper register. the memclk* period is defined by the memclk[2:0] field in the dram config upper register. 8. memreset_l is deasserted after bios sets the dram_init bit in the dram config lower register. this allows time for the pll on registered dimms to stabilize before the deassertion of the dimm ? s reset signal. the delay between these events depends on the silicon revision and the dram operating speed as described in figure 11 and table 26 on page 66. 9. the memcke_lo/up signals are asserted following the deassertion of memreset_l. the delay between these events depends on the silicon revision and the dram operating speed as described in figure 11 and table 26 on page 66. note that the memcke_lo/up delay from memreset_l is different when exiting self-refresh as listed in table 27 on page 66. 66 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 figure 11. memreset_l and memcke_lo/up sequencing table 26. memreset_l and memcke_lo/up initialization timing table 27. memcke_lo/up delay from memreset_l during exit from self-refresh note: refer to the amd opteron ? processor power and thermal data sheet, order# 30417 for silicon revi- sion determination. silicon revision dram speed timing parameter a timing parameter b rev b ddr200 655 s 120ns ddr266 492.8 s 90.2ns ddr333 394.8 s 72.3ns rev c ddr200 163.8 s 491.5 s ddr266 123.2 s 369.6 s ddr333 98.7 s 296.1 s ddr400 81.9 s 245.8 s silicon revision dram speed registered dimms rev b ddr200 120ns ddr266 90.2ns ddr333 72.2ns rev c ddr200 10.24 s ddr266 7.6 s ddr333 6.1 s ddr400 5.1 s dram_init (bios) memreset_l memcke_lo/up a b chapter 7 electrical data 67 23932 rev 3.09 february 2004 amd opteron ? processor data sheet figure 12.power-up signal sequencing pwrok reset_l memreset_l vid[4:0] memcke* clkin_h/l memclk* 01110 (1.2v) va l i d vdd 1 3 6 7 4 8 2 ldtstop_l 5 l0_clkin_h/l[1:0] tms 9 68 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 7.6 reference information notes: 1. clkin_h/l inputs have dc voltage bias generating circuits on the inputs. these consist of both a ~250-ohm pullup resistor to vtt on each input and a ~250-ohm series input resistor. 2. refer to table 5 on page 39 for definitions in pin type column. 3. systems that do not require use of these pins can rely on the internal termination to pull the signals to the proper inactive state. when these pins are used they must not be driven with open-drain outputs or additional termination is required. table 28. internal termination for miscellaneous pins interface pin type 2 internal termination value tolerance clkin_h/l i-iod none 1 fbclkout_h/l o-iod 80-ohm differential termination 50% reset_l i-ios none pwrok i-ios none vid[4:0] o-ios none ldtstop_l i-ios none thermda a none thermdc a none thermtrip_l o-io-od none corefb_h/l a none tck i-ios pullup to vddio 3 533 ohms 50% tms i-ios pullup to vddio 3 533 ohms 50% trst_l i-ios pullup to vddio 3 533 ohms 50% tdi i-ios pullup to vddio 3 533 ohms 50% tdo o-ios pullup to vddio 533 ohms 50% dbreq_l i-ios pullup to vddio 3 533 ohms 50% dbrdy o-ios pullup to vddio 533 ohms 50% chapter 7 electrical data 69 23932 rev 3.09 february 2004 amd opteron ? processor data sheet notes: 1. see the amd athlon ? 64 fx and amd opteron ? processor motherboard design guide , order# 25180, for proper resistor values. 2. input pins of the same type may be pulled high or low through a shared resistor provided that vil max and vih min specifications are not exceeded for those pin types. table 29. external required circuits (pins not normally used in system) pin external circuit (non-operating) 1 nc_g14 tied to vddio_sus through resistor nc_h14 tied to vss through resistor nc_ae14 tied to vddio_run through resistor nc_af13 tied to vddio_run through resistor nc_ae10 tied to vss through resistor nc_ae11 tied to vss through resistor nc_af11 tied to vss through resistor nc_ae13 tied to vss through resistor nc_ae12 tied to vss through resistor nc_t3 tied to vss through resistor nc_t4 tied to vldt through resistor 70 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 7.7 thermal diode specifications an on-die thermal diode is provided as a tool for thermal management. an external sensor is necessary to measure the temperature of the thermal diode. thermal solutions should be not designed and validated using the thermal diode. thermal solutions should be designed and validated against the case temperature specification per the methodology specified in amd athlon tm 64 and amd opteron ? processor thermal guide , order# 26633. table 30. thermal diode specification revision and frequency guide note: refer to the amd opteron ? processor power and thermal data sheet, order# 30417 for silicon revi- sion determination. notes: 1. the sourcing current should always be used in forward bias. 2. characterized at 95 o c with a forward bias current pair of 10 and 100 a. the ideality factor limits correspond to the diode offset limits. 3. temperature offset is unique for each processor. the diode offset value is found in the thermtrip status register discussed in the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? processors, order# 26094. this diode offset supports temperature sensors using two or more sourcing currents only. single- sourcing current implementations are not supported by amd. 4. the temperature offset is set based on a sourcing current pair of 10 and 100 a and an ideality factor of 1.008. the diode offset should be subtracted from the temperature sensor reading. if the temperature sensor has an ideality factor different from 1.008, an additional offset is needed. contact your temperature sensor vendor about whether an additional offset is needed. 5. after correcting for the diode offset, the thermal diode has an accuracy of 10 c. this accuracy is additive to the temperature sensor accuracy. 6. the temperature specification for the processor is based on the case temperature. the thermal resistance from the junction to the case is provided as a reference for implementing fan-speed control using the thermal diode. rev/freq < 2.2ghz >= 2.2ghz b3 table 31 n/a c0 table 31 table 32 cg and later table 32 table 32 table 31. thermal diode specifications for amd opteron ? processor (revision and frequency dependent, see table 30) symbol parameter units min typ max notes i sourcing currents a 5 500 1 n f ideality factor 1.008 1.096 2 t offset temperature offset c 0 32 3, 4, 5 j-c thermal resistance (junction to case) c/w 0.32 6 chapter 7 electrical data 71 23932 rev 3.09 february 2004 amd opteron ? processor data sheet table 32. thermal diode specifications for amd opteron ? processor (revision and frequency dependent, see table 30) notes: 1. the sourcing current should always be used in forward bias. 2. the temperature offset is used to normalize the thermal diode measurement to reflect case temperature at the worst case conditions for a part. 3. this diode offset supports temperature sensors using two or more sourcing currents only. single sourcing current implementations are not supported by amd. 4. the temperature offset is unique for each processor and is programmed at the factory. the diode offset value is found in the thermtrip status register described in the bios and kernel developer ? s guide for the amd athlon ? 64 and amd opteron ? processors, order# 26094. 5. t offset should be subtracted from the temperature sensor reading. if the temperature sensor has an ideality factor different from 1.008, a small correction to this offset is required. contact your temperature sensor vendor to determine if additional correction is required. symbol parameter units min typ max notes i sourcing currents a 5 500 1 t offset temperature offset c 0 52 2, 3, 4, 5 72 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 7.8 power supplies 7.8.1 operating conditions table 33. combined ac and dc operating conditions for power supplies symbol parameter unit min typ max notes vid_vdd vid requested vdd supply level v see note 11 6 vdd_dc vdd supply voltage v vid_vdd ? 50 mv vid_vdd vid_vdd +50 mv vdd_ac vdd supply voltage v vid_vdd ? 100 mv vid_vdd +100 mv 13 vdd_pon vdd supply voltage before pwrok assertion during power-on. v 1.15 1.20 vdd_max 8 vddio_dc vddio supply voltage for ddr333 and below v 2.40 2.50 2.60 10 vddio_dc vddio supply voltage for ddr400 v 2.50 2.60 2.65 10, 12 vddio_ac vddio supply voltage v vddio_dc -150 mv vddio_dc +150 mv 9 vldt vldt supply voltage v 1.14 1.20 1.26 vtt_dc vtt supply voltage v vddio_dc min/2 - 50 mv vddio_dc typ/2 vddio_dc max/2 + 50 mv vtt_ac vtt supply voltage v vtt_dc - 150 mv vtt_dc + 150 mv 9 vdda vdda supply voltage v 2.40 2.50 2.60 idd vdd power supply current a see note 11 iddio1 vddio power supply current a 2.8 2.9 4 iddio2 vddio power supply current in s3 state ma 850 itt1 vtt power supply current ma 200 2, 5 itt2 vtt power supply current in s3 state ma 200 ildt vldt power supply current a 1.5 1 idda vdda power supply current ma 33 iddslew1 vdd power supply current change during normal operation a/ s .0583* f mhz 3, 7 iddslew2 vdd power supply current change upon reset exit a/ s2703 iddslew3 vdd power supply current change upon stop grant entry a/ s ? 270 3 iddslew4 vdd power supply current change upon stop grant exit a/ s2703 chapter 7 electrical data 73 23932 rev 3.09 february 2004 amd opteron ? processor data sheet notes: 1. ildt is specified for three 16x16-bit hypertransport ? links operating at 1.6 gt/s. 2. vtt must both sink and source current. 3. current slew rates are controlled by ramping up or down the core frequency in steps during these sequences to control in-rush currents. 4. vddio current is consumed by i, o, i/o switching current and on-chip functions ( pdl, dll, level-shifters, etc.). 5. vtt current is consumed by i, o, i/o switching current and on-chip functions (pdl, dll, level-shifters, etc.). 6. the processor drives a vid code corresponding to this voltage. 7. for example, the iddslew1 calculation for a 1.2-ghz part is (.0583 x 1200) = 69.96 a/ s. 8. the processor ? s vid[4:0] outputs select vid_pon nom before pwrok is asserted. transients up to vdd_max are allowed. 9. vddio_ac and vtt_ac parameters are measured +/- 1ns of all data bus bits switching. 10. systems designed to ddr400 power supply parameters will also operate correctly with ddr333 and below. 11. refer to the amd opteron tm processor power and thermal data sheet , order# 30417, for these specifications . 12. ddr400 (200mhz) supported by rev c0 and later. refer to the amd opteron ? processor power and thermal data sheet, order# 30417 for silicon revision determination. 13. transient duration below vdd_dc min is limited to < 5 s. transient duration above vdd_dc max is limited to < 2% duty cycle. test by probing differentially at corefb_h and corefb_l with 20mhz scope bandwidth limit. test conditions are while running amd ? s maxpower64 utility using amd thermal approved production grade heat sinks in normal room ambient conditions. 7.8.2 thermal power refer to amd opteron tm processor power and thermal data sheet, order# 30417, for thermal power specifications. 7.8.3 power supply relationships 7.8.3.1 sequencing relationships power supply relationships during power-up, power-down, and entry and exit of any power management state must be controlled in order to avoid damage to the device and help ensure proper operation of the device. figure 13 shows an example of how these relationships can be maintained by system power generation and distribution schemes. pwrok must be deasserted as vdd decays during power down. vtt and vddio are considered suspend planes and are powered in the s0 (working) state and the s1 and s3 sleep states. vdda, vdd, and vldt are considered run planes and are powered in the s0 and s1 states only. all power supplies should be turned off during the s4 (suspend to disk) and s5 (soft-off) states. vddio (run) is a power rail used for pull-ups on some processor signals that connect to devices that are powered off during s3, such as thermtrip_l. iddslew5 vdd power supply current change upon non-reset power failure a/ s ? 4.25 3 table 33. combined ac and dc operating conditions for power supplies symbol parameter unit min typ max notes 74 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 figure 13.sequencing relationships for power supplies table 34. sequencing relationships for power supplies 1. sequencing relationships are measured from supply to supply and cover the dc voltage relationships between supplies that must be maintained under all operating conditions including power up, power down, power failure, and power state transitions in order to avoid device or system damage. these relationships can be maintained by propagation of pwrgd signals from one supply rail to the regulator enable of the next supply. the minimum requirements for a proper system implementation are that: ? vddio ramps such that vddio/2 <= vtt. ? vdd ramps such that vddio and vdda are within spec before vdd is enabled. ? vldt ramps such that vdd is within spec before vldt is enabled. 2. the vtt to vddio relationship allows for vtt to power-up before vddio. 3. the vddio to vtt relationship is critical to avoid overstress of the 2.5-v i/o structures that will occur when vddio exceeds vtt by 1.35 v during normal operation. vtt must track vddio/2 to maintain this specification. during power up and power down vddio may exceed vtt by up to 1.5v for no more than 100ms. 4. the vddio to vdd relationship allows for vddio to power-up before vdd. power supply relationship unit max notes vtt to vddio v vtt_dc max 1, 2 vddio to vtt v vddio_dc max - vtt_dc typ 1, 3 vddio to vdd v vddio_dc max 1, 4 vdda to vdd v vdda max 1, 5 vdd to vldt v vdd max 1, 6 vtt (sus) vddio (sus) vddio (run) vdda (run) vdd (run) vldt (run) power up s3 entry s3 exit power down chapter 7 electrical data 75 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 5. the vdda to vdd relationship allows for vdda to power-up before vdd. vdda must power-up before vdd to ensure that internal clock sources are valid before being used and that clock source multiplexors are properly controlled. 6. the vdd to vldt relationship allows for vdd to power-up before vldt and specifically allows for vdd=vdd_max with vldt=0 v. vdd must power-up before vldt to help ensure that pwrok is properly passed from the pins into the vdd power domain such that the deasserted state can be seen in the vldt power domain. 7.8.3.2 sequencing relationships: signals to power supplies (stress conditions) once the powerup sequence has been completed and pwrok can be asserted, the sequencing of input signals to the cpu and output signals from the cpu can begin. the requirements from signals to power supplies are summarized by type as follows. vddio inputs and outputs are allowed to exceed vddio by 0.3v and are allowed to be 0.3v below vss. vddio inputs are allowed to exceed vtt by vtt_dc max + 0.3v and are allowed to be 0.3v below vss. vldt inputs and outputs are allowed to exceed vldt by 0.3v and are allowed to be 0.3v below vss. 7.8.3.3 power failures the power sequencing relationships defined in sections 7.8.3.1 and 7.8.3.2 must be guaranteed by the motherboard power supply subsystem in the event of a power failure. 7.8.3.4 unused links because the amd opteron processor has three independent hypertransport links, some implementations will not connect one or more of these links. in this case, the vldt of the link that is not connected to another device, should be connected to the vldt of an operating link. note that even if the link is not used, the vldt for the link must be connected so that the internal link detection circuitry can successfully determine the connection status of the link. 76 electrical data chapter 7 amd opteron ? processor data sheet 23932 rev 3.09 february 2004 chapter 8 package specifications 77 23932 rev 3.09 february 2004 amd opteron ? processor data sheet 8 package specifications figure 14. ceramic micro pin grid array package: top, side, and bottom views d1/e1 d2/e2 symbol package wt (gms) bottom view lid side view top view handling and orientation purposes. package that identifies the pin a1 corner and can be used for 3. this corner has a chamfer and a square on top of the 1. all dimensions are specified in millimeters (mm). 4. pin tips should have radius. 2. dimensioning and tolerancing per asme-y14.5m-1994. 5. symbol "m" defines the pin matrix size and "n" is number of pins. 0.25 0.50 b e general notes c l nx?b a2 e2 not to scale a1 c m m c ab k 4 a ccc detail k r b1 a1 corner 3 d2 d a d1 0.81 1.06 0.30 max 2.29 45.17 ref n ccc r m b1 l 940 0.125 2.03 31 max. 1.27 bsc 0.35 40.20 4.88 ref 38.10 bsc 1.796 3.35 variations xucg940 37.6 a1 e b a2 a 1.556 0.275 3.05 37.4 d/e amd 39.80 min. ?b1 (nx plcs) e see notes e1 5 a1 corner |
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